Precision low jitter oscillator circuit
AssigneeGennum Corporation
InventorsWei Yang, Frederick Edward Sykes
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Abstract
A precision, low jitter oscillator circuit is provided that is particularly well-suited for generating a clock signal in miniature digital systems, such as digital hearing aids. The oscillator includes a plurality of differential inverters configured in a feedback loop to generate an oscillating clock signal. The differential inverters include a capacitive trimming network for adjusting the frequency of the oscillating clock signal and employ resistive loads for minimizing jitter in the clock signal. The components of the oscillator are fabricated in a common silicon process to minimize the size of the oscillator.
Claims26
An oscillator, comprising:
- a plurality of differential inverters configured in a feedback loop to generate an oscillating output signal, each differential inverter including a capacitive trimming network;
- and
- a plurality of digital trimming bits coupled to the capacitive trimming networks for selecting one or more capacitors in each capacitive trimming network, wherein the delay of each differential inverter is simultaneously adjusted in response to the digital trimming bits.
A precision, low jitter oscillator for generating an adjustable clock signal, comprising:
- a plurality of differential inverters configured in a feedback loop to generate an oscillating clock signal, each differential inverter including a capacitive trimming network that is coupled to a plurality of digital trimming bits for selecting one or more capacitors in each of the capacitive trimming networks to thereby adjust the frequency of the oscillating clock signal.
Dependencies are inferred from the claim text.