System and method for determining frequency tolerance without a reference
AssigneeApplied Micro Circuits Corporation
InventorPaul Spencer Milton
Life of this patent
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Abstract
A system and method have been provided for determining a frequency tolerance between a generated clock and an input data rate. The invention analyzes beatnotes, externally generated through a comparison of clock and input data rates, and an overflow count of the clock. The occurrence of overflow counts, without intervening beatnotes, indicates that the clock and data rate are close in frequency. The occurrence of beatnotes without intervening overflow counts indicates that the clock and data rates are not close in frequency. Hysteresis is built into the system, preventing the system from indicating an out-of-lock condition when the beatnotes immediate follow the an overflow count, or when the system monitors occasional beatnotes.
Claims18
A method for determining frequency tolerance, the method comprising:
- measuring the frequency of a first signal, wherein measuring the frequency of the first signal includes counting cycles of the first signal;
- accepting a measurement of a difference in frequency between the first signal and a second signal with a data rate;
- reinitializing the measurement of the frequency of the first signal in response to the difference, wherein reinitializing the measurement of the frequency of the first signal includes reinitializing counting cycles of the first signal;
- and
- determining a sufficient tolerance between the first and second signal frequencies in response to completing the measurement of the frequency of the first signal, wherein determining a sufficient tolerance between the first and second signal frequencies includes counting to more than a predetermined first number of cycles to obtain a first count;
- wherein accepting the measurement of the difference in frequency between the first signal and the second signal includes generating a reset signal having a frequency that is the absolute difference in frequency between the first signal frequency and second signal data rate;
- and wherein reinitializing counting cycles of the first signal includes restarting the count at zero in response to the reset signal.
A system for determining frequency tolerance, the system comprising:
- a beatnote regulator having a first input to accept a beatnote signal having a frequency equal to the difference between an oscillator signal frequency and a data signal rate, and an output to provide a reset signal in response to the beatnote signal;
- a counter having a first input to accept and count cycles of the oscillator signal, the counter having an output to provide an overflow signal in response to meeting a first count, and a second input connected to the beatnote regulator output to reinitialize the counter;
- and
- a lock analyzer having a first input connected to the output of the beatnote regulator and a second input connected to the output of the counter, the lock analyzer analyzing the reset and overflow signals to supply a lock signal at a first output when the oscillator and data signal frequencies are within a sufficient tolerance.
Dependencies are inferred from the claim text.