Low headroom current mirror

A current mirror having an input current and an output current, the input and output currents having a defined relationship, the mirror comprising:

• a first and second transistor, each transistor having a gate, drain and source, the gates of each transistor being connected at the same potential and the sources of the two transistors being connected at the same potential, the drain of the second transistor forming the output of the mirror;
• a control element having a first and second input and a first and second output, the first input being connected to the input current of the mirror, the second input being connected to the drain of the second transistor, the first output controlling the potential at the gates of the first and second transistors, and the second output being connected to the drain of the first transistor;
• and
• wherein the outputs of the control element are adapted to force the drain current of the first transistor to match a defined ratio of the input current and the voltage on the drain of the first transistor to match the voltage at the drain of the second transistor, thereby maintaining the defined relationship between the input and output of the mirror.

A circuit comprising:

• a current source providing an input current;
• first and second FET transistors having a common gate voltage and a common source voltage and forming a current mirror, said current mirror generating a mirror current at the drain of the second transistor, said mirror current having a defined relationship with the input current;
• a control element having a first and second input and a first and second output, the first input being connected to the current source, the second input being connected to the drain of the second transistor, the first output being connected to the common gate terminal of the first and second transistor, and the second output being connected to the drain of the first transistor, and
• wherein the control element is adapted to control the drain of the first transistor such that it is at the same potential as the drain of the second transistor, and to control the potential of the common gate terminals such that the drain current of the first transistor has a defined relationship to the input current.