Sense amplifier-based flip-flop with asynchronous set and reset
AssigneeTexas Instruments Incorporated
InventorsWenyan Jia, Borivoje Nikolic
Life of this patent
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Abstract
A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and {overscore (Q)}′. These signals have rising and falling transistors with the same delays for the Q signal and the {overscore (Q)} signal. The second stage has symmetrical pull-up and pull-down circuits.
Claims8
A flip-flop for asynchronous set and reset, comprising:
- a first stage for inputting a differential set of data inputs and generating a differential set of outputs;
- a set and reset second stage for receiving said set of differential set of outputs from said first stage and to output a differential set of outputs including a Q signal and a {overscore (Q)} signal from said set and reset second stage, wherein said signal Q and signal {overscore (Q)} have equal delay times.
A flip-flop for asynchronous set and reset, comprising:
- a first stage for inputting a differential set of data inputs and generating a differential set of outputs;
- a set and reset second stage for receiving said set of differential set of outputs from said first stage and to output a differential set of outputs including a Q signal and {overscore (Q)} signal from said set and reset second stage;
- and
- a circuit to provide asynchronous operation for said first stage.
A flip-flop for asynchronous set and reset, comprising:
- a first stage for inputting a differential set of data inputs and generating a differential set of outputs, said outputs being a set signal and a reset signal;
- a set and reset second stage for receiving said set of differential set of outputs from said first stage and to output a differential set of outputs including a Q signal and a {overscore (Q)} signal from said set and reset second stage;
- and
- a circuit to provide asynchronous operation of said set signal.
A flip-flop for asynchronous set and reset, comprising:
- a first stage for inputting a differential set of data inputs and generating a differential set of outputs, said outputs being a set signal and a reset signal;
- a set and reset second stage for receiving said set of differential set of outputs from said first stage and to output a differential set of outputs including a Q signal and a {overscore (Q)} signal from said set and reset second stage;
- and
- a circuit to provide asynchronous operation of said reset signal.
A flip-flop for asynchronous set and reset, comprising:
- a first stage for inputting a differential set of data inputs and generating a differential set of outputs, said outputs being a set signal and a reset signal;
- a set and reset second stage for receiving said set of differential set of outputs from said first stage and to output a differential set of outputs including a Q signal and a {overscore (Q)} signal from said set and reset second stage;
- and
- a circuit to provide asynchronous operation of said set and reset signals and to prevent short circuit connection when {overscore (Set)} and {overscore (Clear)} are asserted.
Dependencies are inferred from the claim text.