Methods of rerouting dies using antifuses

A method of fabricating a memory device comprising:

• providing a memory chip package;
• providing a logic circuit within said memory chip package including an array of storage cells, an address decoder coupled to said array of storage cells, and a memory controller coupled to said array of storage cells;
• coupling a plurality of contact pins to said memory chip package;
• providing a first signal path having a first segment and a plurality of second segments;
• coupling said first segment of said first signal path to said logic circuit;
• coupling each of said plurality of second segments of said first signal path to a select one of said plurality of contact pins, each of said plurality of second segments independent from one another;
• disposing a routing matrix circuit in-line with said first signal path between said first segment and said plurality of second segments, said routing matrix circuit programmable for each of said plurality of second segments between a first state wherein said first segment is coupled to a select one of said plurality of second segments, and a second state wherein said first segment is decoupled from said select one of said plurality of second segments;
• and
• coupling a programming circuit to said routing matrix circuit, said programming circuit arranged to selectively program said routing matrix circuit between said first and second states for each of said plurality of second segments.

A method of fabricating a memory device die stack comprising:

• providing a first semiconductor die having:
• a first logic circuit including a first array of storage cells, a first address decoder coupled to said first array of storage cells, and a first memory controller coupled to said first array of storage cells;
• a plurality of first die contact pads;
• a plurality of first die signal paths coupling said first logic circuit to said plurality of first die contact pads;
• and
• a first routing matrix circuit coupled between at least one of said plurality of first die signal paths and at least one of said plurality of first die contact pads, said first routing matrix circuit programmable to selectively route any of said plurality of first die signal paths coupled to said routing matrix to any of said plurality of first die contact pads coupled to said first routing matrix circuit;
• providing a second semiconductor die having:
• a second logic circuit including a second array of storage cells, a second address decoder coupled to said second array of storage cells, and a second memory controller coupled to said second array of storage cells;
• a plurality of second die contact pads;
• and
• a plurality of second die signal paths,
• coupling each of said plurality of second die signal paths between a select one of said plurality of second die contact pads and said second die logic circuit;
• stacking said first and second semiconductor dies piggyback;
• and
• coupling each of said plurality of first die contact pads to an associated one of said plurality of second die contact pads.

A method of fabricating a memory device chip stack comprising:

• providing a first semiconductor chip having:
• a first logic circuit including a first array of storage cells, a first address decoder coupled to said first array of storage cells, and a first memory controller coupled to said first array of storage cells;
• a plurality of first chip contact pins;
• a plurality of first chip signal paths coupling said first logic circuit to said plurality of first chip contact pins;
• and
• a first routing matrix circuit coupled between at least one of said plurality of first chip signal paths and at least one of said plurality of first chip contact pins, said first routing matrix circuit programmable to selectively route any of said plurality of first chip signal paths coupled to said routing matrix to any of said plurality of first chip contact pins coupled to said first routing matrix circuit;
• and
• providing a second semiconductor chip having:
• a second logic circuit including a second array of storage cells, a second address decoder coupled to said second array of storage cells, and a second memory controller coupled to said second array of storage cells;
• a plurality of second chip contact pins;
• and
• a plurality of second chip signal paths, each of said plurality of second chip signal paths coupling a select one of said plurality of second chip contact pins to said second chip logic circuit;
• stacking said first and second semiconductor chips piggyback on each other;
• and
• coupling each of said plurality of first chip contact pins to an associated one of said plurality of second chip contact pins.

A method of fabricating a memory chip stack comprising:

• providing a first memory chip package having:
• a first logic circuit including a first array of storage cells, a first address decoder coupled to said first array of storage cells, and a first memory controller coupled to said first array of storage cells;
• a plurality of first chip contact pins coupled to said first memory chip package;
• a plurality of first chip signal paths each coupled between said first logic circuit and a select one of said plurality of first chip contact pins;
• a first chip select signal path coupled to said first logic circuit;
• a programmable routing matrix circuit coupled between said first chip select signal path and two of said contact pins, said routing matrix programmed to route said first chip select signal path to a select one of said two contact pins where the remainder one of said two contact pins define a first chip unused contact pin;
• and
• providing a second memory chip package having:
• a second logic circuit including a second array of storage cells, a second address decoder coupled to said second array of storage cells, and a second memory controller coupled to said second array of storage cells;
• a plurality of second chip contact pins coupled to said second memory chip package;
• a second chip unused contact pin coupled to said second memory chip package;
• a plurality of second chip signal paths including a second chip select signal path each coupled between said second logic circuit and a select one of said plurality of second chip contact pins;
• stacking said first and second memory chip packages piggyback;
• coupling each of said plurality of first chip contact pins to an associated one of said plurality of second chip contact pins such that said first chip select signal path is isolated from said second logic circuit and said second chip select signal path is isolated from said first logic circuit.

A method of fabricating a memory chip stack comprising:

• providing a first memory chip package having:
• a first logic circuit including a first array of storage cells, a first address decoder coupled to said first array of storage cells, and a first memory controller coupled to said first array of storage cells;
• a plurality of first chip contact pins coupled to said first memory chip package;
• a plurality of first chip input/output signal paths coupled to said first logic circuit;
• a programmable routing matrix circuit coupled between said plurality of first chip input/output paths and said plurality of contact pins programmed to route each of said plurality of first chip input/output signal paths to a select one of said plurality of contact pins such that there is at least one first chip unused contact pins;
• and
• providing a second memory chip package having:
• a second logic circuit including a second array of storage cells, a second address decoder coupled to said second array of storage cells, and a second memory controller coupled to said second array of storage cells;
• a plurality of second chip contact pins coupled to said second memory chip package including a plurality of second chip unused contact pins;
• a plurality of second chip input/output signal paths each coupled between said second logic circuit and a select one of said plurality of second chip contact pins;
• stacking said first and second memory chip packages piggyback;
• coupling each of said plurality of first chip contact pins to an associated one of said plurality of second chip contact pins such that said first chip input/output signal paths are isolated from said second logic circuit and said second chip input/output signal paths are isolated from said first logic circuit.