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US 6,633,173 B1Granted
Method and apparatus for testing for latch-up in integrated circuits
AssigneeRenesas Technology America, Inc.
InventorRichard Orban
Life of this patent
Estimating the term…
Abstract
A circuit is tested for latch-up by scanning an optical beam across the surface, supplying power to the integrated circuit, monitoring the power of the power supply, and detecting latch-up in the integrated circuit by capturing an image of the integrated circuit when the power reaches a predetermined threshold. The captured image is compared with a baseline image to determine where latch-up occurs in the circuit.
Claims22
An apparatus for testing a circuit, comprising:
- a scanner for scanning an optical beam across the circuit;
- a power supply for supplying power to the circuit;
- a monitor for monitoring the power of the power supply during the scanning;
- and
- a detector for detecting latch-up in the circuit, wherein when the monitor determines that the power reaches a predetermined threshold, the detector captures an image of the circuit that indicates where latch-up occurs in the circuit.
2 more elements
A method of testing a circuit, comprising the steps of:
- capturing a baseline image of the circuit;
- scanning an optical beam across the surface of the circuit;
- monitoring the power delivered from a power supply to the circuit during the scanning;
- capturing a second image of the circuit when the power reaches a predetermined threshold;
- and
- comparing the baseline image to the second image to determine where latch-up occurs in the circuit.
3 more elements
Dependencies are inferred from the claim text.