Low-capacitance bonding pad for semiconductor device
AssigneeIndustrial Technology Research Institute
InventorsMing-Dou Ker, Hsin-Chin Jiang
Life of this patent
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Abstract
A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.
Claims6
A low capacitance bonding pad structure for a semiconductor device, comprising:
- a substrate having a well;
- a doped region formed in the well as a diffusion region;
- a stack of metal layers alternating with dielectric layers on the doped diffusion region, wherein the metal layers are coupled with one and other by a plurality of via plugs in the dielectric layers;
- an uppermost metal layer positioned on the stack and aligned with the doped diffusion region, wherein the metal layers in the stack are arranged in a mesh arrangement, distributed substantially evenly underneath the uppermost metal layer, and an area of each metal layer in the stack is smaller than that of the uppermost metal layer;
- and
- a passivation layer having a bonding pad opening on the uppermost metal layer for externally electric connection.
Dependencies are inferred from the claim text.