Semiconductor wafer for improved chemical-mechanical polishing over large area features
AssigneeMicron Technology, Inc.
InventorsGurtej Singh Sandhu, Chris Chang Yu
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorsGurtej Singh Sandhu, Chris Chang Yu
Estimating the term…
The present invention is a semiconductor wafer, and a method of fabricating the semiconductor wafer, that reduces dishing over large area features in chemical-mechanical polishing processes. The semiconductor wafer has a substrate with an upper surface, a large area feature formed on the substrate, and a separation layer deposited on the substrate. The separation layer has a top surface and a cavity extending from the top surface towards the upper surface of the substrate. The large area feature is positioned in the cavity of the separation layer, and a support pillar is positioned in the cavity. In one embodiment, the pillar has a base positioned between components of the large area feature and a crown positioned proximate to a plane defined by the top surface of the separation layer. In operation, the pillar substantially prevents the polishing pad of a polishing machine from penetrating into the cavity beyond the top surface of the separation layer.
A microelectronic substrate structure for enhancing the performance of mechanical and/or chemical-mechanical planarizing processes comprising:
A semiconductor wafer used in mechanical and/or chemical-mechanical planarizing of metal layers, comprising:
A microelectronic substrate structure for enhancing the performance of mechanical and/or chemical-mechanical planarizing processes comprising:
Dependencies are inferred from the claim text.