High-voltage transistor with multi-layer conduction region
AssigneePower Integrations, Inc.
InventorsVladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
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Abstract
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.
Claims30
A high voltage field-effect transistor (HVFET) comprising:
- a substrate of a first conductivity type;
- a first region of a second conductivity type disposed in the substrate, the first region having an above region, a below region and a lateral boundary;
- at least one buried region of the first conductivity type sandwiched within the first region between the above and below regions;
- a source diffusion region of the second conductivity type disposed in the substrate, an IGFET channel region being formed between the source diffusion region and the first region;
- a drain diffusion region of said second conductivity type disposed in the first region spaced-apart from the at least one buried region;
- an insulated gate formed over the IGFET channel region.
A high voltage field-effect transistor (HVFET) comprising:
- a substrate of a first conductivity type;
- a source diffusion region of a second conductivity type disposed in the substrate, the source diffusion region having a source fingertip area;
- a first region of the second conductivity type disposed in the substrate spaced-apart from the source diffusion region with an IGFET channel region being formed therebetween, the first region having a pair of drain fingertips areas inter-digitated with the source fingertip area;
- a drain diffusion region of the second conductivity type disposed in the first region,
- a buffer area formed between the source diffusion region and the first region adjacent the source fingertip area, the buffer area being substantially wider than the IGFET channel region;
- an insulated gate disposed above the IGFET channel region;
- at least one buried layer of the first conductivity type disposed within the first region, the at least one buried layer forming two or more JFET channels in the first region.
A high voltage field-effect transistor (HVFET) comprising:
- a substrate of a first conductivity type;
- a first region of a second conductivity type disposed in the substrate, the first region having a laterally extended portion that forms a lateral boundary with the substrate;
- a drain diffusion region of the second conductivity type disposed in the first region and separated from the lateral boundary by the laterally extended portion;
- a source diffusion region of the second conductivity type disposed in the substrate and spaced-apart from the lateral boundary, an IGFET channel region being formed between the source diffusion region and the lateral boundary;
- an insulated gate disposed above the IGFET channel region;
- a buried layer of the first conductivity type disposed in the substrate spaced-apart from the drain diffusion region, the buried layer extending through the laterally extended portion of the first region to beneath the source diffusion region, the buried layer dividing the first region into an above region and a below region, the buried layer having one or more openings which connect the above and below regions.
Dependencies are inferred from the claim text.