Low voltage transient voltage suppressor and method of making
AssigneeSemiconductor Components Industries, LLC
InventorsFrancine Y. Robb, Jeffrey Pearse, David M. Heminger, Stephen P. Robb
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Abstract
A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.
Claims15
A semiconductor device comprising:
- a semiconductor substrate formed with a first trench having a vertical sidewall lined with a dielectric material;
- a gate formed within the first trench for controlling a channel along the vertical sidewall;
- and
- a drain connected to the gate at a bottom surface of the first trench.
A trench MOS transient voltage suppressor device comprising:
- a semiconductor substrate formed with a first trench having a vertical sidewall lined with a dielectric material;
- a gate region formed within the first trench for controlling a conduction channel along the vertical sidewall;
- and
- a drain region contacting the gate region at a bottom surface of the first trench.
Dependencies are inferred from the claim text.