Etching method, semiconductor and fabricating method for the same

A fabricating method for a semiconductor device, comprising the steps of:

• depositing an etching stopper film represented by SiCxHyOz (x>O, y≧O, z≧O) on an interconnection layer formed on a substrate;
• depositing an interlayer insulating film represented by SiCxHyOz (x>O, y≧O, z>O) on the etching stopper film;
• and
• forming a contact hole through the interlayer insulating film by plasma-etching the interlayer insulating film,
• wherein the portion of carbon atoms with respect to silicon atoms in the etching stopper film is larger than the proportion of carbon atoms with respect to silicon atoms in the interlayer insulating film.

A fabricating method for a semiconductor device, comprising the steps of:

• depositing a first interlayer insulating film represented by SiCxHyOz (x<O, y≧O, z≧O) on an interconnection layer formed on a substrate;
• depositing a second interlayer insulating film represented by SiCxHyOz (x>O, y≧O, z>O) on the etching stopper film;
• and
• plasma-etching the second interlayer insulating film and the first interlayer insulating film sequentially, to form a first opening through the second interlayer insulating film, the diameter of the first opening being smaller toward the bottom end, and a second opening through the first interlayer insulating film, the wall of the second opening being vertical to the bottom surface,
• wherein the proportion of carbon atoms with respect to silicon atoms in the first interlayer insulating film is smaller than the proportion of carbon atoms with respect to silicon atoms in the second interlaver insulating film.

A fabricating method for a semiconductor device, comprising the steps of:

• depositing an interlayer insulating film represented by SiCxHyOz (x>0, y≧0, z>0) on a substrate;
• performing first plasma-etching for the interlayer insulating film while blocking or suppressing a carbon component from being eliminated from a surface portion of the interlayer insulating film, to form a first opening in the interlayer insulating film, the diameter of the first opening being smaller toward the bottom end;
• and
• performing second plasma-etching for the interlayer insulating film while facilitating elimination of the carbon component from the surface portion of the interlayer insulating film, to form a second opening under the first opening in the interlayer insulating film, the wall of the first opening being vertical to the bottom surface.

A fabricating method for a semiconductor device, comprising the steps of:

• depositing an interlayer insulating film represented by SiCxHyOz (x>0, y≧O, z>O) and composed of an organic/inorganic hybrid film having low dielectric constant on a substrate;
• forming a silicon oxide film containing no carbon component on a top surface or a surface portion of the interlayer insulating film by reforming a surface portion of the interlayer insulating film;
• forming a resist film made of a chemical amplification resist material on the silicon oxide film;
• and
• subjecting the resist film to pattern exposure and development to form a resist pattern made of the resist film.

A fabricating method for a semiconductor device, comprising the steps of:

• depositing an etching stopper film on an interconnection layer formed on a substrate, and then depositing an interlayer insulating film represented by SiCxHyOz (x>0, y≧O, z>O) and composed of an organic/inorganic hybrid film having low dielectric constant on the etching stopper film;
• forming a contact hole through the interlayer insulating film;
• forming a resist pattern made of a chemical amplification resist material, the resist pattern having an opening for formation of an interconnection groove, and also forming a protection film made of the chemical amplification resist material on the bottom of the contact hole for protecting the etching stopper film;
• and
• plasma-etching the interlayer insulating film using the resist pattern, to form the interconnection groove in the interlayer insulating films,
• wherein the etching stopper film is composed of a material that deactivates the chemical amplification resist material.

A fabricating method for a semiconductor device, comprising the steps of:

• depositing an etching stopper film represented by SiCxHyOz (x>0, y≧O, z≧O) on an interconnection layer formed on a substrate;
• depositing an interlayer insulating film represented by SiCxHyOz (x>0, y≧O, z>O), on the etching stopper film;
• depositing a CMP stopper film on the interlayer insulating film;
• forming a resist pattern having an opening for formation of a contact hole on the CMP stopper film;
• transferring the opening of the resist pattern to the CMP stopper film, and then plasma-etching the interlayer insulating film while eliminating a carbon component from a surface portion of the interlayer insulating film, to form a contact hole through the interlayer insulating film;
• after removal of the resist pattern, depositing a conductive film on the CMP stopper film to fill the contact hole with the conductive film;
• and
• removing a portion of the conductive film exposed on the CMP stopper film by CMP, to form a plug made of the conductive films,
• wherein the proportion of carbon atoms with respect to silicon atoms in the etching stopper film is larger than the proportion of carbon atoms with respect to silicon atoms in the interlayer insulating film.

A fabricating method for a semiconductor device comprising the steps of:

• depositing an etching stopper film represented by SiCxHyOz (x>0, y≧O, z≧O) on a lower interconnection formed on a substrate;
• depositing an interlayer insulating film represented by SiCxHyOz (x>0, y≧O, z>O) on the etching stopper film;
• depositing a CMP stopper film on the interlayer insulating film;
• forming a first resist pattern having an opening for formation of a contact hole on the CMP stopper film;
• transferring the opening of the first resist pattern to the CMP stopper film, and then plasma-etching the interlayer insulating film while eliminating a carbon component from a surface portion of the interlayer insulating film, to form the contact hole through the interlayer insulating film;
• after removal of the first resist pattern, forming a second resist pattern having an opening for formation of an interconnection groove on the CMP stopper film;
• transferring the opening of the second resist pattern to the CMP stopper film, and then plasma-etching the interlayer insulating film while eliminating a carbon component from a surface portion of the interlayer insulating film, to form the interconnection groove in the interlayer insulating film;
• depositing a conductive film on the CMP stopper film to fill the contact hole and the interconnection groove with the conductive film;
• and
• removing a portion of the conductive film exposed on the CMP stopper film by CMP, to form a plug and an upper interconnection made of the conductive film;
• wherein the proportion of carbon atoms with respect to silicon atoms in the etching stopper film is larger than the proportion of carbon atoms with respect to silicon atoms in the interlayer insulating film.