US 6,632,738 B2 · Method of manufacturing semiconductor device

Abstract

An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×1017 cm−2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C.

Claims14

Dependent claims

A method of manufacturing a semiconductor device, wherein a multi-layer Interconnection structure is formed by a damascene method, comprising the steps in sequence of:

forming a first interconnection layer including a first interconnection;
forming an interlayer insulating film on said first interconnection layer;
forming a low dielectric constant film on said interlayer insulating film;
forming a groove for an interconnection in said low dielectric constant film;
forming a via hole between said first interconnection and said groove in said interlayer insulating film;
turning at least a surface layer of said first interconnection amorphous by implanting ions into the bottom of said via hole;
filling said via hole with a conductive material, thereby forming a via;
while said at least a surface layer of said first interconnection is still in an amorphous state, filling said groove with a conductive material, thereby forming a second interconnection layer including a second interconnection in connection with said via;
and
performing annealing after forming said second interconnection layer.

7 more elements

A method of manufacturing a semiconductor device, wherein a multi-layer interconnection structure is formed by a damascene method, comprising the steps of:

forming a first interconnection layer including a first interconnection;
forming an interlayer insulating film on said first interconnection layer;
forming a low dielectric constant film on said interlayer insulating film;
forming a groove for an interconnection in said low dielectric constant film;
forming a via hole between said first interconnection and said groove in said interlayer insulating film;
forming a barrier metal layer on said via hole, said groove and said low dielectric constant film after forming said groove and said via hole;
turning at least a surface layer of said first interconnection amorphous by implanting ions into the bottom of said via hole;
filling said via hole with a conductive material, thereby forming a via;
while said at least a surface layer of said first interconnection is still in an amorphous state, filling said groove with a conductive material, thereby forming a second interconnection layer including a second interconnection in connection with said via;
and
performing annealing after forming said second interconnection layer.

8 more elements

Dependencies are inferred from the claim text.

Method of manufacturing semiconductor device

Life of this patent

Method of manufacturing semiconductor device

Life of this patent

Abstract

Claims14