Semiconductor device

A semiconductor device comprising:

• an SOI semiconductor substrate in which a silicon layer is formed on an insulating film formed on a supporting semiconductor substrate;
• drain and source regions of a MOS transistor formed in a surface of the SOI semiconductor substrate;
• a gate electrode formed on a surface of a channel region of the MOS transistor between said drain and source regions of said semiconductor substrate with a gate insulating film between the gate electrode and the channel region;
• trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of said semiconductor substrate;
• a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of said element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of said MOS transistor;
• a well region formed in a surface of the supporting semiconductor substrate of said SOI semiconductor substrate, a lower end of said conductive material layer being connected to said well region, and
• the upper portion of said conductive material layer being covered with the insulating film formed on the surface of said element isolation region.

A semiconductor device comprising:

• a memory cell array including an arrangement of MOS transistors for memory cells formed on a semiconductor substrate;
• a peripheral circuit region formed on said semiconductor substrate;
• a plurality of trench type element isolation regions formed in the memory cell array and the peripheral circuit region, the element isolation regions having trenches formed in a surface of said semiconductor substrate, and
• a conductive material layer for a back gate electrode, which is embedded in the trench at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under a channel region of the MOS transistor or to voltage-control the semiconductor substrate region.

A semiconductor memory device comprising a vertical MOS transistor including:

• a semiconductor substrate;
• a first conductive type element region defined in the semiconductor substrate, the element region constituting a channel region;
• first and second gate electrodes embedded in first and second trenches formed to sandwich the element region, the first and second gate electrodes opposing to side surfaces of the element region;
• first and second gate insulation films provided between the first gate electrode and the element region and the second gate electrode and the element region, respectively;
• a second conductive type drain diffusion layer formed on a surface of said element region;
• and
• a second conductive type source diffusion layer embedded in semiconductor substrate in a predetermined depth.

A manufacturing method of a semiconductor memory device, comprising:

• forming an element forming region defined by an element isolation insulating film in a semiconductor substrate;
• ion-implanting impurities in said semiconductor substrate;
• forming a source diffusion layer adjacent to a bottom of said element forming region;
• forming at least two trenches at a predetermined distance in said element forming region;
• forming gate insulating films on side surfaces of an element channel region sandwiched by said two trenches;
• embedding first and second gate electrodes in said trenches;
• and
• forming a drain diffusion layer on the surface of said element channel region.