Method of fabricating variable length vertical transistors

A method of forming vertical CMOS devices, with variable channel lengths, on a semiconductor substrate, comprising the steps of:

• providing a first region of said semiconductor substrate to accommodate an N channel (NMOS) device, and providing a second region of said semiconductor substrate to accommodate a P channel (PMOS) device;
• forming an N type drain region for said NMOS device, in a top portion of said first region of said semiconductor substrate, and forming a P type drain region for said PMOS device, in a top portion of said second region of said semiconductor substrate;
• depositing a first silicon oxide layer on said semiconductor substrate;
• depositing a first silicon nitride layer on said first silicon oxide layer;
• performing a patterning procedure to remove a portion of said first silicon nitride layer from said first silicon oxide layer in said second region of said semiconductor substrate;
• depositing a second silicon nitride layer on said first silicon nitride layer in said first region of said semiconductor substrate, and on said first silicon oxide layer in said second region of said semiconductor substrate;
• depositing a second silicon oxide layer on said second silicon nitride layer;
• forming an NMOS channel opening in said second silicon oxide layer, in said second silicon nitride layer, in said first silicon nitride layer, and in said first silicon oxide layer, exposing a portion of a top surface of said N type drain region, and forming a PMOS channel opening in said second silicon oxide layer, in said second silicon nitride layer, and in said first silicon oxide layer, exposing a portion of a top surface of said P type drain region;
• performing a selective epitaxial deposition of silicon to form a first silicon shape in said NMOS channel opening, and to form a second silicon shape in said PMOS channel opening;
• depositing a first intrinsic polysilicon layer on said first and second silicon shapes;
• performing ion implantation procedures to convert a first portion of said first intrinsic polysilicon layer, located overlying said first silicon shape, to a first N type polysilicon region, and to convert a second portion of said first intrinsic polysilicon layer, located overlying said second silicon shape, to a first P type polysilicon region;
• depositing a third silicon oxide layer on said first N type polysilicon region and said first P type polysilicon region;
• forming photoresist shapes on said third silicon oxide layer, and on said first and second silicon shapes performing an anisotropic reactive ion etch (RIE), by using photoresist shapes as masks;
• to remove portions of said third silicon oxide layer to form silicon oxide hard mask shapes;
• to remove portions of said first N type and first P type polysilicon regions to define an N type polysilicon source shape in said first region of said semiconductor substrate, and to define a P type polysilicon source shape in said second region of said semiconductor substrate;
• and to remove portions of said second silicon oxide layer to define silicon oxide spacers removing said photoresist shapes;
• performing a wet etch procedure to remove said second silicon nitride layer and said first silicon nitride layer to expose a portion of said first silicon shape to be used as an NMOS channel region in said first region of semiconductor substrate, and exposing a portion of said second silicon shape to be used as a PMOS channel region in said second region of said semiconductor substrate, wherein said NMOS channel region having a larger channel length than said PMOS channel region;
• performing a thermal oxidation procedure to grow a silicon dioxide gate insulator layer on said NMOS channel region and on said PMOS channel region, and to grow a silicon oxide layer on exposed sides of said N type polysilicon source shape, and on exposed sides of said P type polysilicon source shape;
• depositing a thick, second intrinsic polysilicon layer on said first silicon oxide layer;
• performing ion implantation procedures to convert a first portion of said thick, second intrinsic polysilicon layer to a thick N type polysilicon region, and to convert a second portion of said thick, second intrinsic polysilicon layer to a thick P type polysilicon region;
• and
• performing an anisotropic dry etch procedure by using said silicon oxide hard mask shapes as an etch mask to remove portions of said thick N type polysilicon region and to remove portions of said thick P type polysilicon region, thereby forming an N type self-aligned polysilicon gate structure in said first region of said semiconductor substrate, and forming a P type self-aligned polysilicon gate structure in said second region of said semiconductor substrate.