Method and apparatus for patching problematic instructions in a microprocessor using software interrupts

An apparatus for processing instructions within a pipelined processor, the apparatus comprising:

• fetching means for fetching an instruction;
• matching means for matching an instruction using at least one match condition, wherein the match condition identifies instructions which are to be placed;
• marking means for marking an instruction as a matched instruction by setting a match bit;
• passing means for passing the match bit associated with the matched instruction through the pipelined processor with the matched instruction;
• replacing means for replacing the matched instruction with an interrupt instruction;
• and
• patching means for patching the marked instruction, using an interrupt handler based on the interrupt instruction, by replacing the marked instruction with one or more other instructions that perform a same logical operation on data as the marked instruction.

A computer program product in a computer-readable medium for use in a data processing system for processing instructions within a pipelined processor, the computer program product comprising:

• instructions for fetching an instruction;
• instructions for matching a fetched instruction using at least one match condition, wherein the match condition identifies instructions which are to be patched;
• instructions for marking an instruction as a matched instruction by setting a match bit;
• instruction for passing the match bit associated with the matched instruction through the pipelined processor with the matched instruction;
• instructions for replacing the matched instruction with an interrupt instruction;
• and
• instructions for patching the marked instruction, using an interrupt handler based on the interrupt instruction, by replacing the marked instruction with one or more other instructions that perform a same logical operation on data as the marked instruction.

A method for processing instructions within a pipelined processor, the method comprising the steps of:

• fetching an instruction;
• matching the instruction based on an opcode of the instruction;
• setting a match bit based on a result of the matching;
• selecting one of the opcode of the instruction and an interrupt opcode based on the value of the match bit and whether or not an interrupt mode is selected, wherein the selected opcode is output as a selected opcode;
• and
• outputting the match bit and the selected opcode to an instruction scheduling unit.

An apparatus for processing instructions within a pipelined processor, comprising:

• an instruction match facility;
• an instruction cache coupled to the instruction match facility;
• an instruction decode unit coupled to the instruction cache;
• and
• an instruction scheduling unit coupled to the instruction decode unit, wherein the instruction match facility matches a fetched instruction based on an opcode of the fetched instruction and outputs opcode instruction bits along with a match bit to the instruction cache, the instruction cache outputs the match bit and the opcode instruction bits to the instruction decode unit, the instruction decode unit selects one of the opcode of the instruction and an interrupt opcode based on the match bit and the assertion of an interrupt mode select signal, the selected opcode being output to the instruction scheduling unit along with the match bit.