Method and apparatus for scheduling memory calibrations based on transactions

A memory controller that controls access to memory comprising:

• a read queue in which transactions seeking to read data from memory are queued;
• a write queue in which transactions seeking to write data to memory are queued;
• temperature calibration logic, including a timer, that initiates temperature calibration cycles to memory;
• a temperature calibration queue in which temperature calibration cycles are queued;
• arbitration logic that determines priority associated with each queue, wherein said arbitration logic causes all transactions pending in said read queue to execute prior to the temperature calibration cycle, and said arbitration logic causes said temperature calibration cycle to begin executing prior to transactions in the write queue;
• and
• wherein said arbitration logic schedules one or more transactions pending in the write queue to execute during idle periods in the temperature calibration cycle.

A computer system, comprising:

• a processor;
• system memory coupled to said processor;
• means for controlling access to said system memory, said means for controlling including means for queuing read transactions to said system memory, means for queuing write transactions to said system memory, means for queuing calibration cycles to said system memory, and means for queuing operational cycles to system memory, and
• wherein said means for controlling further includes an arbiter that prioritizes transactions pending in each of said queue means so that transactions pending in said read transaction queue means execute first, and transactions pending in said calibration queue execute second.

A method for controlling access to memory, comprising:

• sorting memory transactions into a read queue, a write queue, a calibration queue, and an operational queue;
• executing transactions pending in the read queue prior to executing other transactions;
• executing any transaction pending in said calibration queue, prior to executing transactions pending in the write queue or the operational queue;
• and
• scheduling transactions pending in the write queue or the operational queue to execute during idle periods in the calibration cycle.