VLIW computer processing architecture with on-chip dynamic RAM

A processor chip, comprising:

• a processing core;
• at least one bank of DRAM memory;
• an I/O link configured to communicate with other like processor chips or compatible I/O devices;
• a memory controller in electrical communication with said processing core and said at least one bank of memory;
• a distributed shared memory controller in electrical communication with said memory controller and said I/O link;
• and
• an external memory interface in electrical communication with said memory controller;
• said distributed shared memory controller configured to control the exchange of data between said processor chip and said other of said one or more processor chips or I/O devices;
• said external memory interface configured to connect said processor chip in electrical communication with external memory;
• said memory controller configured to receive memory requests from said processing core and said distributed shared memory controller, determine whether said memory requests are directed to said at least one bank of memory on said processor chip or to said external memory, and process said memory requests with said at least one bank of DRAM memory or with said external memory through said external memory interface.

In a computer system, a scalable computer processing architecture, comprising:

• one or more processor chips, each comprising:
• a processing core;
• at least one bank of memory;
• an I/O link configured to communicate with other of said one or more processor chips or with compatible I/O devices;
• a memory controller in electrical communication with said processing core and said at least one bank of memory;
• a distributed shared memory controller in electrical communication with said memory controller and said I/O link;
• and
• an external memory interface in electrical communication with said memory controller;
• said distributed shared memory controller configured to control the exchange of data between said processor chip and said other of said one or more processor chips or I/O devices;
• said external memory interface configured to connect said one or more processor chips in electrical communication with external memory;
• said memory controller configured to receive memory requests from said processing core and said distributed shared memory controller, determine whether said memory requests are directed to said at least one bank of memory on said one or more processor chips or to said external memory, and process said memory requests with said at least one bank of memory or with said external memory through said external memory interface;
• wherein said computer processing architecture can be scaled larger by connecting together two or more of said processor chips in parallel via said I/O links of said processor chips, so as to create multiple processing core pipelines which share data therebetween.

A processor chip, comprising:

• a processing core;
• at least one bank of DRAM memory;
• an I/O link configured to communicate with other like processor chips or compatible I/O devices;
• a memory controller in electrical communication with said processing core and said at least one bank of memory;
• and
• a distributed shared memory controller in electrical communication with said memory controller and said I/O link, said distributed shared memory controller comprising a first communication engine and a second communication engine;
• said first communication engine configured to receive I/O requests or data messages from said processing core destined for one or more processor chips or I/O devices and communicate the I/O requests or data messages to the one or more processor chips or I/O devices;
• said second communication engine configured to receive I/O requests from one or more processor chips or I/O devices and communicate the I/O requests with the processing core or the memory controller;
• said memory controller configured to receive memory requests from said processing core and said distributed shared memory controller, and process said memory requests with said at least one bank of DRAM memory.

In a computer system, a scalable computer processing architecture, comprising:

• a first processor chip and a second processor chip, each comprising:
• a processing core;
• at least one bank of memory;
• an I/O link configured to communicate with other of said one or more processor chips or with compatible I/O devices;
• a memory controller in electrical communication with said processing core and said at least one bank of memory;
• and
• a distributed shared memory controller in electrical communication with said memory controller and said I/O link;
• wherein a memory request directed from said processing core on said first processor chip to said at least one bank of memory on said second processor chip is processed by:
• said processing core on said first processor chip sending a memory request to said memory controller on said first processor chip;
• said memory controller on said first processor chip determining that said memory request is not destined to said at least one bank of memory on said first processor chip, and passing said memory request to said distributed shared memory controller on said first processor chip;
• said distributed shared memory controller on said first processor chip passing said memory request to said distributed shared memory controller on said second processor chip via said I/O links on said first and said second processor chips;
• said distributed shared memory controller on said second processor chip passing said memory request to said memory controller on said second processor chip;
• said memory controller on said second processor chip processing said memory request with said at least one bank of memory on said second processor chip, performing a memory access function;
• said memory controller on said second processor chip passing a result of said memory access function back to said distributed shared memory controller on said second processor chip;
• said distributed shared memory controller on said second processor chip passing said result of said memory access function back to said distributed shared memory controller on said first processor chip via said I/O links on said first and said second processor chips;
• said distributed shared memory controller on said first processor chip passing said result of said memory access function to said memory controller on said first processor chip;
• and
• said memory controller on said first processor chip communicating said result of said memory access function to said processing core on said first processor chip.