Three-dimensional memory array incorporating serial chain diode stack

An integrated circuit comprising:

• a multi-level programmable memory array comprising a plurality of parallel, spaced-apart conductors on each level of the memory array, forming memory cells at each intersection between conductors of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell;
• wherein the respective directionality of memory cells in at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed;
• and
• wherein memory cells in at least one pair of adjacent memory planes share conductors disposed between said pair of adjacent memory planes.

An integrated circuit comprising:

• a multi-level programmable memory array comprising a plurality of parallel, spaced-apart rail-stacks on each level of the memory array, forming memory cells at each intersection between rail-stacks of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell;
• wherein the respective directionality of memory cells in at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed;
• and
• wherein memory cells in at least one pair of adjacent memory planes share rail-stacks disposed between said pair of adjacent memory planes.

An integrated circuit comprising:

• a three-dimensional memory array including
• alternating levels of X-lines and Y-lines;
• plural memory planes, each plane comprising passive element memory cells formed respectively at intersections between X-lines of one level and Y-lines of an adjacent level, each memory cell having a respective directionality;
• wherein at least two adjacent memory planes are both associated with the respective level of X-lines or Y-lines disposed therebetween;
• and
• wherein the respective directionalities of memory cells on said at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed.

An integrated circuit comprising:

• a multi-level programmable memory array comprising a plurality of conductors on at least three levels of the memory array, forming a passive element memory cell at each intersection between conductors of adjacent levels, each cell having a respective directionality;
• and
• programming circuits for driving a selected conductor on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected conductor, and to a second programming voltage if the selected memory plane is disposed below the selected conductor;
• wherein the respective directionality of memory cells on at least two adjacent levels are oriented alike.

An integrated circuit comprising:

• a multi-level programmable memory array comprising a plurality of parallel, spaced-apart conductors on each level of the memory array, forming memory cells at each intersection between conductors of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell;
• and
• programming circuits for driving a selected conductor on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected conductor, and to a second programming voltage if the selected memory plane is disposed below the selected conductor;
• wherein the respective directionality of memory cells on at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed.

An integrated circuit comprising:

• a multi-level programmable memory array comprising a plurality of parallel, spaced-apart rail-stacks on each level of the memory array, forming memory cells at each intersection between rail-stacks of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell;
• and
• programming circuits for driving a selected rail-stack on a level of the memory array to a first programming voltage if the selected rail-stack is connected to a selected memory cell anode terminal, and to a second programming voltage if the selected rail-stack is connected to a selected memory cell cathode terminal;
• wherein the respective directionality of memory cells on at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed.

An integrated circuit comprising:

• a multi-level programmable memory array comprising a plurality of parallel, spaced-apart rail-stacks on each level of the memory array, forming memory cells at each intersection between rail-stacks of adjacent levels, each cell including a steering device, at least once programmed, which gives a respective directionality to each cell;
• and
• programming circuits for driving a selected rail-stack on a level of the memory array to a first programming voltage if a memory plane selected for programming is disposed above the selected rail-stack, and to a second programming voltage if the selected memory plane is disposed below the selected rail-stack;
• wherein the respective directionality of memory cells on at least two adjacent memory planes are oriented in the same direction relative to a substrate upon which the array is formed.