Controlled voltage monostable circuit
AssigneeSTMicroelectronics S.r.l.
InventorsGiulio Corva, Ignazio Bellomo
Life of this patent
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Abstract
The present invention relates a monostable circuit adapted to provide a delay having a length inversely proportional to an input signal, characterized by comprising generating means (21, 22) adapted to generate a signal proportionally to an input signal (Vin) and to a corrective factor (35), comparing means (23) adapted to compare the value of said signal with a prefixed value range (Imin, Imax) and correcting means (24) adapted to correct said corrective factor (35) in the case that the value of said signal is out of said prefixed value range (Imin, Imax).
Claims16
A monostable circuit for providing a delay that is inversely proportional to an input signal, comprising:
- means for generating a signal proportional to an input signal and to a corrective factor;
- means for comparing the value of said generated signal with a prefixed value range;
- and
- means for correcting said corrective factor if the value of said generated signal is out of said prefixed value range.
A method for generating a delay having a length inversely proportional to signal, comprising:
- a) generating a signal proportionally to an input signal and to a corrective factor;
- b) comparing the value of said generated signal with a prefixed value range;
- and
- c) correcting said corrective factor in the case that said generated signal is out of said prefixed value range.
A DC-to-DC buck converter circuit comprising:
- a divider having an input for receiving an input signal and an output;
- a monostable circuit for providing a delay inversely proportional to and having a switching frequency independent of said input signal, having an input coupled to the output of the divider, and an output;
- a logic block having an input coupled to the output of the monostable circuit, and an output;
- a power block having an input coupled to the output of the logic block, and an output for providing an output voltage;
- and
- a comparator in communication with said power block for providing feedback to said logic block.
Dependencies are inferred from the claim text.