Digitally controlled analog delay locked loop (DLL)
AssigneeCypress Semiconductor Corporation
InventorTimothy E. Fiscus
Life of this patent
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Abstract
An apparatus comprising an analog delay line and a control circuit. The analog delay line may be configured to generate an output signal in response to an input signal, a first control signal, and a second control signal. A phase of the output signal may be (i) coarsely adjustable with respect to the input signal in response to the first control signal and (ii) finely and continuously adjustable in response to the second control signal. The control circuit may be configured to generate the first and the second control signals in response to the input signal and the output signal.
Claims16
An apparatus comprising:
- an analog delay line (i) comprising (a) a delay chain comprising a plurality of delay elements each comprising a plurality of delay cells and amplifiers and (b) a shift register and (ii) configured to generate an output signal in response to an input signal, a first control signal, and a second control signal, wherein a phase of said output signal is (i) coarsely adjustable with respect to said input signal in response to said first control signal and (ii) finely and continuously adjustable in response to said second control signal;
- and
- a control circuit configured to generate said first and said second control signals in response to said input signal and said output signal.
An apparatus comprising:
- means for generating an output signal in response to an input signal, a first control signal, and a second control signal, wherein a phase of said output signal is (i) coarsely adjusted with respect to said input signal by selecting a number of delay elements in response to said first control signal and (ii) finely and continuously adjustable in response to said second control signal;
- means for generating said first and said second control signals in response to said input signal and said output signal;
- and
- means for controlling a presentation of data by a memory device in response to said output signal.
A method for locking and adjusting a phase of an output signal to a phase of an input signal comprising the steps of:
- (A) generating an output signal in response to an input signal, a first control signal, and a second control signal, wherein a phase of said output signal is (i) coarsely adjusted with respect to said input signal by selecting a number of delay elements in response to said first control signal and (ii) finely and continuously adjustable in response to said second control signal;
- (B) generating said first and said second control signals in response to said input signal and said output signal;
- and
- (C) controlling a presentation of data by a memory device in response to said output signal.
Dependencies are inferred from the claim text.