Firmware mechanism for correcting soft errors
AssigneeIntel Corporation
InventorNhon Quach
Life of this patent
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AssigneeIntel Corporation
InventorNhon Quach
Estimating the term…
A computer system includes processor having dual execution cores and a non-volatile memory that stores an error recovery routine. The processor's execution cores operate in lock step when the processor is in a redundant execution mode, and they operate independently when the processor is in a split execution mode. The error recovery routine is invoked when the processor detects a soft error while operating in the redundant execution mode. The error recovery routine switches the processor to split execution mode. In split mode, each execution core saves uncorrupted processor state data to a designated memory location and updates any corrupted data with corresponding processor state data from the other execution core. The error recovery routine returns the processor to redundant mode, initializes each execution core with the recovered processor state data, and returns control of the processor to the program thread that was executing when the soft error was detected.
A computer system, comprising:
A method for handling soft errors in a processor capable of operating first and second execution cores in redundant and split modes, the method comprising:
A machine readable medium on which are stored instructions that are executable by a dual execution core processor to implement a method for recovering from soft errors, the method comprising:
A computer system comprising:
A computer system, comprising:
A computer system, comprising:
Dependencies are inferred from the claim text.