Back to results
US 6,624,699 B2Granted
Current-controlled CMOS wideband data amplifier circuits
AssigneeBroadcom Corporation
InventorsGuangming Yin, Jun Cao
Life of this patent
Estimating the term…
Abstract
Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.
Claims31
An amplifier stage comprising:
- a current source;
- a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source;
- a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source;
- a first series peaking inductor having positive and negative ends, wherein the negative end of the first series peaking inductor is coupled to the gate of the first differential transistor;
- a second series peaking inductor having positive and negative ends, wherein the negative end of the second series peaking inductor is coupled to the gate of the second differential transistor;
- a first output resistor having positive and negative ends, wherein the negative end of the first output resistor is coupled to the drain of the first differential transistor;
- a second output resistor having positive and negative ends, wherein the negative end of the second output resistor is coupled to the drain of the second differential transistor;
- a first shunt peaking inductor having positive and negative ends, wherein the negative end of the first shunt peaking inductor is coupled to the positive end of the first output resistor;
- and
- a second shunt peaking inductor having positive and negative ends, wherein the negative end of the second shunt peaking inductor is coupled to the positive end of the second output resistor.
7 more elements
An amplifier stage comprising:
- a current source;
- a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source;
- a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source;
- a first series peaking inductor having positive and negative ends, wherein the negative end of the first series peaking inductor is coupled to the gate of the first differential transistor;
- a second series peaking inductor having positive and negative ends, wherein the negative end of the second series peaking inductor is coupled to the gate of the second differential transistor;
- a first shunt peaking inductor coupled in series with a first output resistor and coupled to the drain of the first differential transistor;
- a second shunt peaking inductor coupled in series with a second output resistor and coupled to the drain of the second differential transistor.
4 more elements
A multi-stage differential amplifier comprising:
- a first amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
- and
- a last amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
- wherein the positive signal output of the first amplifier stage is coupled to the positive signal input of the last amplifier stage, and wherein the negative signal output of the first amplifier stage is coupled to the negative signal input of the last amplifier stage;
- wherein one of the first amplifier stage and last amplifier stage includes a first pair of series peaking inductors;
- wherein one of the first amplifier stage and last amplifier stage includes a first pair of shunt peaking inductors;
- and
- wherein one of the first amplifier stage and last amplifier stage includes a first pair of miller capacitance cancellation capacitors.
5 more elements
A multi-stage differential amplifier comprising:
- a first amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
- an intermediate amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
- and
- a last amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
- wherein the positive signal output of the first amplifier stage is coupled to the positive signal input of the intermediate amplifier stage, and wherein the negative signal output of the first amplifier stage is coupled to the negative signal input of the intermediate amplifier stage;
- wherein the positive signal output of the intermediate amplifier stage is coupled to the positive signal input of the last amplifier stage, and wherein the negative signal output of the intermediate amplifier stage is coupled to the negative signal input of the last amplifier stage;
- wherein one of the first amplifier stage, intermediate amplifier stage, and last amplifier stage includes a first pair of series peaking inductors;
- wherein one of the first amplifier stage, intermediate amplifier stage, and last amplifier stage includes a first pair shunt peaking inductors;
- and
- wherein one of the first amplifier stage, intermediate amplifier stage, and last amplifier stage includes a first pair of miller capacitance cancellation capacitors.
7 more elements
A multi-stage differential amplifier comprising:
- a first amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
- a plurality of intermediate amplifier stages, the plurality having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
- and
- a last amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
- wherein the positive signal output of the first amplifier stage is coupled to the positive signal input of the plurality of intermediate amplifier stages, and wherein the negative signal output of the first amplifier stage is coupled to the negative signal input of the plurality of intermediate amplifier stages;
- wherein the positive signal output of the plurality of intermediate amplifier stages is coupled to the positive signal input of the last amplifier stage, and wherein the negative signal output of the plurality of intermediate amplifier stages is coupled to the negative signal input of the last amplifier stage;
- wherein one of the first amplifier stage, plurality of intermediate stages, and last amplifier stage includes a first pair of series peaking inductors;
- wherein one of the first amplifier stage, plurality of intermediate amplifier stages, and last amplifier stage includes a first pair of shunt peaking inductors;
- and
- wherein one of the first amplifier stage, plurality of intermediate amplifier stages, and last amplifier stage includes a first pair of miller capacitance cancellation capacitors.
7 more elements
A multistage differential amplifier comprising:
- a plurality of stages each having a differential input and a differential output;
- wherein a bandwidth of at least one stage is increased by shunt inductors placed in series with each of a pair of output load resistors;
- and
- wherein a bandwidth of at least one stage is increased by series inductors placed in series with the stage's differential input.
1 more element
A multistage differential amplifier comprising:
- a first stage comprising:
- a first differential pair having a first output node and a second output node;
- a first series combination including a first resistor and first inductor coupled to the first output node;
- and
- a second series combination including a second resistor and second inductor coupled to the second output node;
- and
- a second stage comprising:
- a second differential pair having a first input node and a second input node;
- a third inductor in series with the first input node;
- and
- a fourth inductor in series with the second input node.
8 more elements
Dependencies are inferred from the claim text.