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US 6,624,688 B2Granted
Filtering variable offset amplifer
AssigneeIntel Corporation
InventorsJames E. Jaussi, Bryan K. Casper, Aaron K. Martin
Life of this patent
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Abstract
A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.
Claims28
A filtering method comprising:
- receiving first and second differential inputs, the second input having been received prior to the first input;
- biasing first and second differential input pairs with the first and second differential inputs, respectively;
- weighting the first and second differential inputs by modulating a gain of at least one of the differential input pairs;
- and
- tapping first and second output nodes to obtain a filtered signal, wherein the first and second output nodes are connected to transistors of the differential input pairs which are biased by inverted inputs and non-inverted inputs, respectively.
2 more elements
A communications system comprising:
- (a) a transmitter producing a differential voltage signal;
- (b) a receiver comprising:
- (1) a sample-and-hold circuit that receives the differential voltage signal and samples and holds values of the differential voltage signal;
- and
- (2) a filter circuit comprising:
- a first differential transistor pair biased by a first differential input received from the sample-and-hold circuit;
- a second differential transistor pair biased by a second differential input, the second differential input having been received from the sample-and-hold circuit prior to the first differential input;
- at least one current source coupled to provide tail currents for the differential transistor pairs;
- wherein the transistors which are biased by present and previous inverted inputs have a first output terminal;
- and
- wherein the transistors which are biased by present and previous non-inverted inputs have a second output terminal.
8 more elements
A filter circuit comprising:
- a first differential transistor pair biased by a first differential input;
- a second differential transistor pair biased by a second differential input, the second differential input having been received prior to the first differential input;
- at least one current source coupled to provide tail currents for the differential transistor pairs, said tail current of the first differential transistor pair being different from said tail current of the second differential transistor pair;
- wherein the transistors which are biased by present and previous inverted inputs have a first output node;
- wherein the transistors which are biased by present and previous non-inverted inputs have a second output node;
- and
- wherein the tail current differential is provided by a difference in channel widths between the first and second differential transistor pairs.
4 more elements
A filter circuit comprising:
- a first differential transistor pair biased by a first differential input;
- a second differential transistor pair biased by a second differential input, the second differential input having been received prior to the first differential input;
- at least one current source coupled to provide tail currents for the differential transistor pairs;
- first and second offset-inducing differential pairs connected in parallel to the first and second differential transistor pairs, respectively;
- wherein the transistors which are biased by present and previous inverted inputs have a first output node;
- and
- wherein the transistors which are biased by present and previous non-inverted inputs have a second output node.
4 more elements
A filter circuit comprising:
- a first differential transistor pair biased by a first differential input;
- a second differential transistor pair biased by a second differential input, the second differential input having been received prior to the first differential input;
- at least one current source coupled to provide tail currents for the differential transistor pairs;
- wherein the transistors which are biased by present and previous inverted inputs have a first output node;
- wherein the transistors which are biased by present and previous non-inverted inputs have a second output node;
- end
- wherein the transistors of the differential transistor pairs are p-channel MOSFET transistors;
- and
- wherein a filtered output signal is provided at the output nodes.
6 more elements
A filter circuit comprising:
- a first differential transistor pair biased by a first differential input;
- a second differential transistor pair biased by a second differential input, the second differential input having been received prior to the first differential input;
- a third differential transistor pair being biased by a third differential input received after the first differential input;
- at least one current source coupled to provide tail currents for the differential transistor pairs;
- wherein the transistors which are biased by present and previous inverted inputs have a first output node;
- and
- wherein the transistors which are biased by present and previous non-inverted inputs have a second output node.
4 more elements
Dependencies are inferred from the claim text.