Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices
AssigneeAdvanced Micro Devices, Inc.
InventorHyeon-Seag Kim
Life of this patent
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Abstract
A method for reducing off-state leakage current of a MOSFET while promoting the formation of an epitaxial gate insulator layer between the substrate and gate stack includes implanting source/drain dopant into the substrate, and then forming a very thin epitaxial Silicon layer on the substrate by, e.g., molecular beam epitaxy. The high-k gate insulator layer is then deposited on the epitaxial layer, without an interfering native oxide or interfacial oxide being formed between the insulator layer and substrate, while establishing a very steep retrograde dopant profile and hence reducing off-state leakage current through the channel region.
Claims3
A MOSFET device, comprising:
- a silicon substrate having a flat top surface and having source/drain regions and a channel region between said source/drain regions, wherein said source/drain regions and said channel region are formed under said top surface of said substrate;
- a gate stack;
- a gate insulator layer between the substrate and the gate stack;
- and
- an epitaxial silicon layer between the gate insulator layer and the substrate, wherein said gate insulator layer is formed of a high-k insulator comprising titanium oxide (TiO2) and in direct contact with said epitaxial silicon layer, and
- wherein said epitaxial silicon layer is formed on and in direct contact with said top surface of said substrate after forming said source/drain regions, and said epitaxial silicon layer has a thickness of from 20 Angstroms to 30 nanometers and is patterned to have a substantially same width as that of said gate stack and said gate insulator layer in a gate length direction.
Dependencies are inferred from the claim text.