Method and apparatus for utilizing write buffers in memory control/interface

An apparatus comprising:

• a set of buffers to store one or more write commands and their corresponding write data received from a first device,
• the corresponding write data being delayed by the first device by a first delay period,
• wherein, upon receiving another write command from the first device,
• one of the one or more write commands stored in the set of buffers is translated into a buffered write command, and
• the buffered write command and its corresponding data are sent to a second device for execution, without waiting for the write data of said another write command to be sent from the first device.

A memory control unit comprising:

• a first memory controller to issue read and write commands to access a first memory device, the first memory controller to defer write data transfer on a write command for a period corresponding to a read latency of a previously issued read command;
• wherein the first memory device requiring write data to be sent with a write command to execute a write operation to store the respective write data into the first memory device;
• and
• a translator unit coupled to the first memory controller and the first memory device to provide signal translation between the first memory controller and the first memory device to facilitate memory transactions between the first memory controller and the first memory device, the translator unit including
• a set of buffers to store one or more write commands and their corresponding write data received from the first memory controller,
• the translator unit to send a buffered write command and its corresponding write data to the first memory device for execution upon receiving another write command from the first memory controller, without waiting for the write data corresponding to said another write command to be sent from the first memory controller.

A system comprising:

• one or more processors;
• a system memory;
• and
• a memory control unit coupled to the one or more processors and the system memory, the memory control unit comprising:
• a memory controller;
• and
• a translator unit coupled between the memory controller and the system memory, the translator unit to provide an interface between the memory controller and the system memory, the translator unit comprising:
• a set of buffers to store write commands and corresponding write data received from the memory controller, a write command and its corresponding write data stored in the set of buffers being sent to the system memory for execution, upon receiving another write command from the memory controller and without waiting for the write data corresponding to the another write command to be sent from the memory controller.