Interpolation looping of prioritized audio samples in cache connected to system bus
AssigneeCreative Technology Ltd
InventorDavid P. Rossum
Life of this patent
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Abstract
A cache memory is updated with audio samples in a manner which minimizes system bus bandwidth and cache size requirements. The end of a loop is used to truncate a normal cache request to exactly what is needed. A channel with a loopEnd in a request will be given higher priority in a two-stage priority scheme. The requested data is conformed by trimming to the minimum data block size of the bus, such a doubleword for a PCI bus. The audio data written into the cache can be shifted on a byte-wise basis, and unneeded bytes can be blocked and not written. Request data for which a bus request has been issued can be preempted by request data attaining a higher priority before a bus grant is received.
Claims9
A method for updating a cache memory having multiple channels storing digital audio waveform samples for further processing, by updating with data from a main memory over a bus, comprising:
- determining a cache invalid size for a channel corresponding to a number of cache memory locations no longer required for said further processing;
- detecting the occurrence of a loop end;
- when said cache invalid size extends beyond said loop end, prior to calculation of a new current address, calculating a new current address by subtracting a loop size from said loop end;
- and
- requesting data from said main memory across said bus up to said loop end with subsequent data from a loop start address.
A cache memory system having multiple channels storing digital audio samples, coupled to a bus, comprising:
- channel address logic configured to determine a cache invalid size for a channel corresponding to a number of cache memory locations no longer required for further processing, and to detect the occurrence of a loop end;
- request logic configured to generate a request to fetch data corresponding to said cache invalid size only up to said loop end when said cache invalid size extends beyond said loop end, prior to calculation of a new current address, and fetch subsequent data from a loop start address;
- and
- logic for calculating a new current address by subtracting a loop size from said loop end.
A cache memory system for updating a cache memory storing digital audio waveform samples for multiple channels, using a shared bus, comprising:
- request logic configured to provide a set of request parameters for updating a channel in said cache memory in accordance with a priority scheme;
- accept logic configured to request access to said shared bus and to replace said set of request parameters in accordance with a change in priority between requesting access to said shared bus and a grant of access.
Dependencies are inferred from the claim text.