US 6,621,427 B2 · Method and apparatus for implementing a doubly balanced code

Abstract

One embodiment of the present invention provides a system for encoding a dataword into a current codeword within a stream of codewords, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions. The system creates the current codeword from the dataword and a preceding codeword in the stream by inverting substantially half of the zero bits of the preceding codeword and inverting substantially half of the one bits of the preceding codeword. This is accomplished by using the dataword to select one bits and the zero bits to invert; determining locations of the one bits and zero bits in the preceding codeword; and then inverting the selected one bits and zero bits in the preceding codeword to form the current codeword. Note that because the present invention balances rising and falling transitions without significantly increasing pin requirements, it achieves most of the electrical advantages of differential signaling along with most of the pin-efficiency of single-ended signaling. Moreover, by having substantially half the bits change at each transition, it is possible to determine timing information from transitions in the codeword, without the need for a separate clock signal.

Claims24

Dependent claims

A method for encoding a dataword into a current codeword in a stream of codewords, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions, the method comprising:

receiving the dataword;
and
creating the current codeword from the dataword and a preceding codeword in the stream by inverting substantially half of the zero bits of the preceding codeword and inverting substantially half of the one bits of the preceding codeword;
wherein inverting substantially half of the zero bits and substantially half of the one bits involves,
using the dataword to select one bits and the zero bits to invert,
determining locations of the one bits and zero bits in the preceding codeword, and
inverting the selected one bits and zero bits in the preceding codeword to form the current codeword.

4 more elements

An apparatus that encodes a dataword into a current codeword in a stream of codewords, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions, the method comprising:

an input that is configured to receive the dataword and a preceding codeword in the stream of codewords;
and
an inverting circuit that is configured to create the current codeword from the dataword and the preceding codeword inverting substantially half of the zero bits of the preceding codeword and inverting substantially half of the one bits of the preceding codeword;
wherein the inverting circuit is configured to,
use the dataword to select one bits and the zero bits to invert,
determine locations of the one bits and zero bits in the preceding codeword, and to
invert the selected one bits and zero bits in the preceding codeword to form the current codeword.

4 more elements

A method for decoding a current codeword into a dataword, the method comprising:

receiving a stream of codewords, including a preceding codeword and the current codeword, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions;
identifying a pattern of bits that have been inverted in the preceding codeword to produce the current codeword;
and
translating the pattern of bits that have been inverted into the dataword, wherein the translation uses a predefined mapping between inversion patterns for bits in the preceding codeword and bit patterns for the dataword.

1 more element

An apparatus for decoding a current codeword into a dataword, comprising:

an input that is configured to receive a stream of codewords, including a preceding codeword and the current codeword, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions;
an identification circuit that is configured to identify a pattern of bits that have been inverted in the preceding codeword to produce the current codeword;
and
a translation circuit that is configured to translate the pattern of bits that have been inverted into the dataword based on a predefined mapping between inversion patterns for bits in the preceding codeword and bit patterns for the dataword.

1 more element

Dependencies are inferred from the claim text.

Method and apparatus for implementing a doubly balanced code

Life of this patent

Method and apparatus for implementing a doubly balanced code

Life of this patent

Abstract

Claims24