Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect

A method for designing circuit layout of non-neighboring bit lines to reduce coupling effect in sensing operation, said method comprising:

• providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent said bit lines are paired using in sensing operation of a memory cell in said memory array;
• and
• separating a first pair of bit lines by inserting one of a second pair of said bit lines into said first pair of bit lines in layout design,
• whereby coupling effect is reduced by non-neighboring bit line layout of said memory array in sensing operation.

A method for designing circuit layout of non-neighboring bit lines to reduce coupling effect in sensing operation, said method comprising:

• providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent said bit lines are paired using in sensing operation of a memory cell in said memory array;
• assigning a first pair of said bit lines permuted with each other in layout design;
• and
• extending layout space between said permuted first pair of bit lines,
• whereby said bit lines adjacent to said permuted first pair of bit lines are not assigned sequentially, and coupling effect is reduced by non-neighboring bit line layout of said memory array in sensing operation.

A method for designing circuit layout of non-neighboring bit lines to reduce coupling effect in sensing operation, said method comprising:

• providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent said bit lines are paired using in sensing operation of a memory cell in said memory array;
• and
• separating a first pair of said bit lines by inserting a second pair of said bit lines into said first pair of bit lines in layout design,
• whereby coupling effect is reduced by non-neighboring bit line layout of said memory array in sensing operation.