Estimating capacitance effects in integrated circuits using congestion estimations

A computer system for estimating capacitance effects in interconnects to be routed in an integrated circuit, using a design simulating the integrated circuit prior to the routing, the design comprising a plurality of metal layers in an area, the computer system comprising:

• means for retrieving from memory, capacitance effects for the area in each metal layer;
• means for retrieving from memory, interconnect densities for each metal layer;
• means for normalizing the interconnect densities for each metal layer;
• and
• means for multiplying the normalized interconnect density for each metal layer with the retrieved capacitance effect for the area in the corresponding metal layer.

A computer-implemented method for estimating capacitance effects in interconnects to be routed in an integrated circuit using a design that simulates the integrated circuit prior to the routing, the method comprising:

• retrieving from memory, interconnect densities for each metal layer;
• normalizing the interconnect densities, for each metal layer;
• determining a probability that an interconnect hypothetically routed in a metal layer of the design has neighboring interconnects in an area;
• using the probability obtained from said determining to retrieve from memory capacitance effects for each metal layer in said area;
• multiplying the normalized interconnect density for each metal layer, with capacitance effect for said area in the corresponding metal layer;
• and
• summing the products of said act of multiplying for metal layers that share a common interconnect direction.