Method for evaluating decoupling capacitor placement for VLSI chips
AssigneeInternational Business Machines Corporation
InventorsAllan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
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Abstract
A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
Claims17
A storage medium encoded with machine readable computer program code for evaluating decoupling capacitance in an integrated chip, the storage medium including instructions for causing a processor to implement a method comprising:
- analyzing a macro of said integrated chip to predict a magnitude of a current transient generated by switching circuits of said macro;
- determining a required decoupling capacitance as a function of said current transient of said macro;
- processing a model of said integrated chip eliminating hierarchal aspects to generate a floor planned model including a plurality of macros;
- and
- ascertaining from said floor planned model whether an available decoupling capacitance for each instance of each macro of said plurality of macros is sufficient.
Dependencies are inferred from the claim text.