Configuration and method for producing test signals for testing a multiplicity of semiconductor chips

A method for producing test signals for testing a plurality of semiconductor chips having signal inputs, which comprises:

• supplying test signals to semiconductor chips in a precise temporal sequence with respect to a clock signal;
• determining from the clock signal the temporal sequence of the test signals on each of the semiconductor chips;
• connecting latches downstream of each of the signal inputs for each of the test signals;
• supplying the clock signal to a delay locked loop unit;
• and
• using the clock signal with the delay locked loop unit to produce a delayed clock signal to activate the latches.

A configuration for producing test signals for testing a plurality of semiconductor chips each having at least one signal input, comprising:

• means for supplying test signals to semiconductor chips in a precise temporal sequence with respect to a clock signal;
• means for determining from the clock signal the temporal sequence of the test signals on each of the semiconductor chips;
• latches connected downstream of each of the at least one signal input for each of the test signals;
• and
• a delay locked loop unit for using the clock signal to produce a delayed clock signal to activate said latches.