US 6,618,832 B1 · Method and bus interface employing a memory in an intergrated circuit which is used to link a bus with an application device to be controlled by the bus

Abstract

The IEEE1394 bus communication protocol has three layers: physical layer, link layer, and transaction layer. A link layer IC implements the interface to an external application and prepares data for sending on the bus, or interprets incoming data packets from the IEEE1394 bus. A physical layer IC implements the direct electrical connection to the bus and controls many functions including arbitration for sending data on the bus. According to the invention the capacity of the on-chip memory becomes assigned in a flexible way in order to be able to meet the requirements for any specific service. Further, the on-chip memory is prevented from storing data packets containing transmission errors by CRC checking on the fly header data and other data. This is performed for asynchronous data packets as well as isochronous data packets, and allows to have a minimum on-chip memory capacity only.

Claims8

Dependent claims

Method for employing a memory in an integrated circuit which is used to link a bus with an application device to be controlled by said bus, including the steps:

sending asynchronous or isochronous data packets via said bus to said application device which data packets include header data to which a first error protection code is assigned and payload data to which a second error protection code is assigned, wherein said payload data are intended to be intermediately stored in said memory;
evaluating in each case for a received current data packet said first error protection code, wherein, if this evaluation indicates that the header data of the current data packet have been received erroneously, at least payload data of the current data packet are not written into said memory;
and
overwriting the header data of the current data packet in said memory with the header data of the next data packet to be received, if header data of said current data packet have been written previously into said memory and the evaluation of said first error protection code or said second error protection code, respectively, indicates that the header data resp. payload data of the current data packet have been received erroneously.

1 more element

Dependencies are inferred from the claim text.

Method and bus interface employing a memory in an intergrated circuit which is used to link a bus with an application device to be controlled by the bus

Life of this patent

Method and bus interface employing a memory in an intergrated circuit which is used to link a bus with an application device to be controlled by the bus

Life of this patent

Abstract

Claims8