System and method for parallel testing of IEEE 1149.1 compliant integrated circuits

A method of testing a plurality of integrated circuits comprising:

• receiving a plurality of test data signals from a plurality of integrated circuits under evaluation;
• adding a delay to the plurality of test data signals to synchronize the plurality of test data signals with a system clock;
• selecting a subset of the plurality of test data signals;
• simultaneously comparing the subset of the plurality of test data signals with a reference signal;
• and
• determining whether each of the test data signals comprising the subset of test data signals is the same as the reference signal.

A parallel integrated circuit test unit comprising:

• means for receiving a plurality of test data signals from an integrated circuit under evaluation;
• means for selecting a subset of the plurality of test data signals;
• means for synchronizing the subset of the plurality of test data signals responsive to timing delays;
• and
• means for comparing the subset of the plurality of test data signals with a master reference signal.