Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs
AssigneeCadence Design Systems, Inc.
InventorsXinghao Chen, Joseph C. Watkins
Life of this patent
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Abstract
A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described. With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences so that when they are applied, all outputs of embedded RAMs attain known values.
Claims11
A method for improving the efficiency of test sequences for testing logic having a multiple port random access memory (RAM) embedded therein, the RAM having at least one read port and one write port, the read port having a plurality of output terminals and address input terminals and the write port having a plurality of data input terminals and address input terminals, the method comprising the steps of:
- a) applying an initial test sequence to a plurality of inputs of the logic;
- b) identifying which of the outputs of the at least one read port have an indeterminate value;
- and
- c) setting each of the outputs of the at least one read port having an indeterminate value to a known value by:
- c1) forcing the address input terminals of the at least one read port to read a first word at a first address such that the first word read appears at the output terminals of the at least one read port;
- and in the event where step c1) fails to set the outputs of the at least one read port having an indeterminate value to a known value, performing step c2) by
- c2) writing a second word at a second address accessible to the at least one write port and forcing the read address terminal of the at least one read port to read the second word, wherein the second written word appears at the output terminals of the at least one read port.
A method for improving the efficiency of test sequences for testing logic having a plurality of multiple port random access memories (RAMs) embedded therein, each of the RAMs having at least one read port and one write port, the read port having a plurality of output terminals and address input terminals and the write port having a plurality of data input terminals and address input terminals, the method comprising the steps of:
- a) applying an initial test sequence to a plurality of inputs of the logic;
- b) identifying which of the outputs of at least one of the read port of each of the RAMs have an indeterminate value;
- and
- c) setting each of the outputs of the at least one read port in each of the RAMs having an indeterminate value to a known value by:
- c1) forcing the address input terminals of the at least one read port to read a first word at a first address such that the first word read appears at the output terminals of the at least one read port;
- and in the event where step c1) fails to set the outputs of the at least one read port having an indeterminate value to a known value, performing step c2) by
- c2) writing a second word at a second address accessible to the at least one write port and forcing the read address terminal of the at least one read port to read the second word, wherein the second written word appears at the output terminals of the at least one read port.
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method claims for improving the efficiency of test sequences for testing a random access memory (RAM) array embedded in logic, the RAM having at least one read port and one write port, the read port having a plurality of output terminals and address input terminals and the write port having a plurality of data input terminals and address input terminals, the method steps comprising:
- a) applying an initial test sequence to a plurality of inputs of the logic;
- b) identifying which of the outputs of the at least one read port have an indeterminate value;
- and
- c) setting each of the outputs of the at least one read port having an indeterminate value to a known value by:
- c1) forcing the address input terminals of the at least one read port to read a first word at a first address such that the first word read appears at the output terminals of the at least one read port;
- and in the event where step c1) fails to set the outputs of the at least one read port having an indeterminate value to a known value, performing step c2) by
- c2) writing a second word at a second address accessible to the at least one write port and forcing the read address terminal of the at least one read port to read the second word, wherein the second written word appears at the output terminals.
Dependencies are inferred from the claim text.