Superscalar processing system and method for selectively stalling instructions within an issue group

A computer processing system for efficiently processing instructions of computer programs, comprising:

• an instruction dispersal unit configured to receive instructions of a computer program and to define issue groups based on said received instructions, said instruction dispersal unit further configured to transmit said issue groups, each of said issue groups including instructions to be simultaneously processed by said system, said instruction dispersal unit configured to ensure that each instruction of said issue groups is free of data dependencies with any of the other instructions of the same issue group;
• a plurality of pipelines configured to receive said instructions of said issue groups from said instruction dispersal unit, wherein each of said instructions is processed by a different one of said pipelines with respect to each of the other instructions in the same issue group;
• and
• a control mechanism configured to determine to stall an instruction in one of said issue groups in response to a determination that said stalled instruction is dependent on unavailable data, said control mechanism further configured to selectively stall other instructions in said one issue group based on an age of each of the other instructions in said one issue group with respect to said stalled instruction.

An in-order superscalar processing method for efficiently processing instructions of computer programs, comprising the steps of:

• receiving instructions from a computer program;
• defining issue groups based on said instructions, each of said issue groups including instructions that may be simultaneously processed;
• sequentially transmitting said issue groups to a plurality of pipelines;
• simultaneously processing each instruction in one of said issue groups via a corresponding stage of a different one of said pipelines;
• stalling a first instruction in said one issue group;
• enabling processing of other instructions in said one issue group while said first instruction is stalled in said stalling step;
• and
• selectively stalling other instructions in said one issue group based on an age of each selectively stalled instruction with respect to an age of said first instruction.

An in-order superscalar processing method for efficiently processing instructions of computer programs, comprising the steps of:

• receiving instructions from a computer program;
• defining issue groups based on said instructions, each of said issue groups including instructions that may simultaneously execute within a computer processor, said defining step comprising the step of ensuring that each instruction of said issue groups is free of data dependencies with any of the other instructions of the same issue group;
• processing said issue groups in stages within said computer processor;
• stalling an instruction in said one issue group;
• enabling other instructions in said one issue group to advance to another stage while said instruction is stalled by said stalling step;
• and
• selectively stalling other instructions in said one issue group based on said stalling an instruction step thereby ensuring that said instructions of said computer program complete execution in program order.

A superscalar processing system, comprising:

• a plurality of pipelines, each of said pipelines having a plurality of stages;
• an instruction dispersal unit configured to receive instructions and to define an issue group based on said received instructions, said issue group including a plurality of instructions to be successively executed by said pipelines in program order, each of said instructions to be simultaneously processed by a corresponding stage of a different one of said pipelines;
• and
• a control mechanism configured to initiate a stall of one of said instructions in response to a determination that said one instruction is dependent on unavailable data, said control mechanism configured to stall each instruction in said issue group that is younger than said one instruction during said stall of said one instruction, wherein said control mechanism is further configured to enable further processing, by one of said pipelines during said stall of said one instruction, an instruction of said issue group that is older than said one instruction.