Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information

A method for implementing two types of architectures on a chip, comprising:

• (a) receiving an instruction from a fetch engine,
• (b) determining whether the instruction is a macroinstruction or a microinstruction,
• (c) if the instruction is a macroinstruction,
• (i) sending the macroinstruction to an emulation engine,
• (ii) decomposing the macroinstruction into one or more microinstructions,
• (iii) bundling the one or more microinstructions into at least one bundle with a bundler, wherein the bundle includes a template that specifies the type of data in the bundle, and wherein the bundler
• receives at least one sequence of instructions (an “XUOP”),
• determines how many XUOPs are received, and
• when more than one XUOP is received,
• determines whether the XUOPs must be issued in parallel, and
• when the XUOPs must be issued in parallel, issues a plurality of the bundles containing the XUOPs to the execution engine in parallel,
• when the XUOPs need not be issued in parallel, determines whether a particular problem exists, and
• when the problem does not exist, dispatches a plurality of the bundles containing the XUOPs to the execution engine in parallel,
• when the problem does exist, dispatches a plurality of the bundles containing one of the XUOPs to the execution engine,
• when only one XUOP is received, determines whether the one XUOP must be issued in parallel with another XUOP, and
• when the one XUOP must be issued in parallel, dispatches nothing to the execution engine,
• when the one XUOP need not be issued in parallel, dispatches the bundle containing the one XUOP to the execution engine, and
• (iv) dispatching the at least one bundle in parallel to an execution engine, the step of dispatching comprising dispatching a plurality of the bundles containing the XUOPs when a plurality of XUOPs are received and must be issued in parallel, and
• (d) if the instruction is a microinstruction, dispatching the microinstruction to the execution engine.

A computer system with a processor, comprising:

• a fetch engine,
• an emulation engine, comprising
• a queue,
• a bundler, and
• an emulation front end,
• an execution engine, and
• a buffer capable of receiving instructions from the fetch engine or the emulation engine and delivering instructions to the execution engine, wherein the bundler:
• receives sequences of instructions from the emulation front end,
• converts each of the sequences into a plurality of bundles, each of the bundles including a template that specifies a type of data contained the bundle,
• determines whether a plurality of the instructions must be issued in parallel, and
• delivers the plurality of bundles to the execution engine, wherein the bundles are delivered in parallel when the instructions must be issued in parallel and when a particular problem exists.