Procedure and processor arrangement for parallel data processing
AssigneeSystemonic AG
InventorsMatthias Weiss, Gerhard Fettweis
Life of this patent
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Abstract
A procedure and a processor arrangement for parallel data processing in which data are read out from a data memory and are conveyed via a communications unit to processing units for parallel processing. The data are divided into data groups with several elements and are stored in a group memory under a common address. To each data group, a processing unit is allocated, in that at least one element of a data group can be directly linked to the allocated processing unit, directly bypassing the communications unit. In a parallel fashion, a data group is read out from the data memory and is distributed over one or several processing units and is processed in a parallel fashion in the latter.
Claims12
A method for parallel data processing in which data are read out from a data memory and are conveyed via a communications unit to processing units for parallel processing, comprising:
- dividing data into data groups with several elements stored under a common memory address;
- allocating a processing unit to each element of a data group, with at least one element of the data group linked directly with the allocated processing unit;
- and
- reading a data group from data memory for processing in parallel by the processing units.
A processor arrangement for parallel data processing, comprising:
- a data memory, the data memory storing at least one data group with several elements under one address;
- a communications unit coupled to the data memory and having a width which is smaller than the number of elements in one data group;
- a plurality of parallel processing units, which are linked to each other via the communications unit, each processing unit including at least one process unit and a plurality of memory units which are arranged in a strip which is adjacent to at least one further strips with the same structure;
- wherein each element of the data group is allocated a part of the overall communications unit and a processing unit and wherein the data memory is linked directly with the memory elements of an allocated processing unit in the width of a one element of one data group within one strip.
Dependencies are inferred from the claim text.