System and method for controlling power states of a memory device via detection of a chip select signal

A memory system, comprising:

• at least one memory device for storing data;
• a memory controller that sends data and signals to the at least one memory device;
• a chip select line that connects the memory controller and the at least one memory device, or a portion thereof, the chip select line allowing the transmission of a chip select signal to the at least one memory device, or the portion thereof, the chip select signal selecting the at least one memory device, or the portion thereof, to sample commands;
• and
• an edge detection device implementing logic for detecting an edge of an assertion of the chip select signal, wherein when the logic detects the edge of the chip select signal provided to the at least one memory device, or the portion thereof, that is in a power state lower than its active state, the at least one memory device, or the portion thereof, is automatically moved from the lower power state to a higher power state, and all clock inputs to the at least one memory device, or the portion thereof, are disabled to conserve power when the at least one memory device, or the portion thereof, is in the lower power state.