Method and system for managing a PCI bus coupled to another system
AssigneeHewlett-Packard Development Company, L.P.
InventorPeter J. Hammersley
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Abstract
The present invention provides a PCI bus switching architecture to allow a pair of PCI processors to have access to a common set of PCI I/O cards. More specifically, this design allows either cross-coupled processor to dynamically take over the operational controls of the common set of PCI I/O cards if the primary processor for the same become inoperative. The present invention achieves the objective by employing a point to point data link connection between each processor and their respective controllers for each common set of PCI I/O cards associated with a PCI bus.
Claims20
A method for a first processor that controls I/O traffic of a first PCI bus to acquire and relinquish control of a second PCI bus when a second processor for doing the same becomes inoperative, each processor includes at least one primary and back-up I/O controller, the process comprising:
- recognizing inoperative state of the second processor to control a second PCI bus;
- deactivating the primary I/O controller of the inoperative second processor by switching the primary I/O controller of the second processor into a high impedance state to thereby prevent the flow of I/O traffic between the second PCI bus and the second processor;
- activating the back-up I/O controller of the first processor;
- and
- managing the second PCI bus with the active back-up I/O controller of the first processor while the primary I/O controller of the first processor continues to manage the first PCI bus.
A network switching architecture, comprising:
- a first and a second processor coupled by an interconnect;
- a first and a second set of I/O cards;
- a first and a second PCI bus respectively coupled to the first and second set of I/O cards;
- a first and a second master hot swap controller (“mHSC”) respectively coupled to the first and second processor;
- a first, second, third, and fourth PCI controller respectively coupled between the first PCI bus and the first mHSC, the second PCI bus and the second mHSC, first mHSC and the second PCI bus, and the second mHSC and the first PCI bus;
- a first, second, third, and fourth data link respectively coupled between the first PCI controller and the first processor, the second PCI controller and the first processor, the third PCI controller and the second processor, and the fourth PCI controller and the second processor;
- and
- a first, second, third, and fourth slave hot swap controller (“sHSC”) respectively coupled between the first PCI controller and the first mHSC, the second PCI controller and the first mHSC, the third PCI controller and the second mHSC, and the fourth PCI controller and the second mHSC.
A method for a first processor that controls I/O traffic of a first PCI bus to acquire and relinquish control of a second PCI bus when a second processor for doing the same becomes inoperative, each processor includes at least one primary and back-up I/O controller, the process comprising:
- recognizing inoperative state of the second processor to control a second PCI bus;
- deactivating the primary I/O controller of the inoperative second processor;
- activating the back-up I/O controller of the first processor;
- powering down the inoperative second processor by an external high availability mechanism;
- and
- managing the second PCI bus with the active back-up I/O controller of the first processor while the primary I/O controller of the first processor continues to manage the first PCI bus.
A method for a first processor that controls I/O traffic of a first PCI bus to acquire and relinquish control of a second PCI bus when a second processor for doing the same becomes inoperative, each processor includes at least one primary and back-up I/O controller, the process comprising:
- recognizing inoperative state of the second processor to control a second PCI bus;
- deactivating the primary I/O controller of the inoperative second processor,
- activating the back-up I/O controller of the first processor;
- powering down an inoperative peripheral device of the second PCI bus;
- and
- managing the second PCI bus with the active back-up I/O controller of the first processor while the primary I/O controller of the first processor continues to manage the first PCI bus.
Dependencies are inferred from the claim text.