US 6,618,780 B1 · Method and apparatus for controlling interrupt priority resolution

Abstract

A method and apparatus are described which allow for greater control of interrupt generation to a processor or the like. In one embodiment, a priority selection device is provided which allows a processor or other devices to set the relative priorities among different interrupt requests. The priority information may be dynamic in that it can be modified at other times (e.g., based on the needs of the computer system). A priority resolution device and mask logic device determine which of the generated interrupt requests is of the highest priority and generates an interrupt to the processor to service that high-priority interrupt. In one embodiment, when a processor is servicing an interrupt and a higher priority interrupt is generated, the processor nests the servicing of the higher-priority interrupt in the servicing of the current interrupt. If the newly asserted interrupt request has a priority that is less than the priority of the currently serviced interrupt, the lower-priority interrupt is prevented from being asserted to the processor (until at least the servicing of the higher-priority interrupt is complete, for example).

Claims13

Dependent claims

A computer system comprising:

a plurality of interrupt sources;
a processor operable for servicing interrupt requests generated by the interrupt sources;
a priority selection device for storage of a plurality of available IRQ source numbers according to assigned priority levels, comprising a first plurality of sequentially ordered priority level registers, each representing an IRQ priority level and storing an IRQ source number assigned to the IRQ priority level;
and
a priority resolution device coupled to said processor and said priority selection device, said priority resolution device comprising:
a plurality of sequentially ordered first multiplexers, each comprising:
a plurality of inputs, each coupled to receive a signal representing a status of an IRQ;
a select input coupled to receive the IRQ source number stored in a corresponding one of the priority level registers;
and
an output representing the status of the IRQ assigned to the corresponding one of the priority level registers;
and
an encoder, comprising:
a plurality of inputs, each coupled to receive the output from one of the plurality of multiplexers;
and
an output representing the level of a selected IRQ having the highest priority level of IRQs with an active status.

12 more elements

A priority interrupt resolution system for a computing system, comprising:

a priority selection device, comprising:
a first plurality of sequentially ordered priority level registers, each representing an IRQ priority level and storing an IRQ source number assigned to the IRQ priority level;
a priority resolution device, comprising:
a plurality of sequentially ordered first multiplexers, each comprising:
a plurality of inputs, each coupled to receive a signal representing a status of an IRQ;
a select input coupled to receive the IRQ source number stored in a corresponding one of the priority level registers;
and
an output representing the status of the IRQ assigned to the corresponding one of the priority level registers;
and
an encoder, comprising:
a plurality of inputs, each coupled to receive the output from one of the plurality of multiplexers;
and
an output representing the level of a selected IRQ having the highest priority level of IRQs with an active status;
and
a second multiplexer, comprising:
a plurality of inputs, each coupled to receive the IRQ source number stored in a corresponding one of the priority level registers;
a select input coupled to receive the output of the encoder;
and
an output representing the IRQ source number of the selected IRQ;
whereby a processor may execute an interrupt service routine of the selected IRQ.

17 more elements

Dependencies are inferred from the claim text.

Method and apparatus for controlling interrupt priority resolution

Life of this patent

Method and apparatus for controlling interrupt priority resolution

Life of this patent

Abstract

Claims13