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US 6,618,462 B1Granted
Digital frequency divider
AssigneeGlobespanVirata, Inc.
InventorsJohn M. Ross, Peter Keller
Life of this patent
Estimating the term…
Abstract
A system and method is presented for dividing a reference clock frequency by any real number. The invention allows for a real number divisor that could have any desired degree of precision. Additionally, the invention seeks to minimize hardware complexity in realizing such a reference-clock frequency divider. In one particular embodiment of the invention, a system and method is presented, wherein the real number divisor is a real number having a repeating decimal (i.e., the real number may be represented by a fraction).
Claims56
A system for dividing clock frequencies, comprising:
- a reference clock configured to generate a reference clock signal having a reference clock frequency;
- a multi-phase clock generator configured to generate a finite number of clock signals from the reference clock signal, wherein each of the finite number of clock signals has the same frequency, wherein each of the finite number of clock signals is offset from each of the other finite number of clock signals by a phase offset, wherein the phase offset between adjacent clocks within the finite number of clocks is the same;
- a real number divisor comprising an integer portion and a decimal portion, wherein the decimal portion comprises a remainder portion having a finite degree of precision and an error portion, wherein the finite degree of precision of the remainder portion is proportional to the finite number of clock signals;
- an error accumulator configured to accumulate an error term, wherein the accumulated error represents a part of the real number that is not reflected in the finite number of clock signals;
- and
- a glitch-free multiplexer configured to receive the finite number of clock signals, wherein the glitch-free multiplexer is further configured to receive a clock select signal, wherein the glitch-free multiplexer is further configured to select a clock signal from the finite number of clock signals in response to the received clock select signal, wherein the glitch-free multiplexer is further configured to output the selected clock signal, wherein the clock select signal is a function of the integer portion of the real number, wherein the clock select signal is further a function of the remainder portion of the real number, wherein the clock select signal is further a function of the accumulated error.
3 more elements
A system for dividing clock frequencies, comprising:
- a reference clock configured to generate a reference clock signal having a reference clock frequency;
- a multi-phase clock generator configured to generate a finite number of clock signals from the reference clock signal;
- a real number divisor comprising an integer portion and a decimal portion, wherein the decimal portion comprises a remainder portion having a finite degree of precision, wherein the finite degree of precision of the remainder portion is proportional to the finite number of clock signals;
- an error accumulator configured to accumulate an error term, wherein the accumulated error represents a part of the real number that is not reflected in the finite number of clock signals;
- and
- a glitch-free multiplexer configured to receive the finite number of clock signals and a clock select signal, wherein the glitch-free multiplexer is further configured to select a clock signal from the finite number of clock signals in response to the received clock select signal, wherein the glitch-free multiplexer is further configured to output the selected clock signal as a function of the integer portion of the real number.
3 more elements
A system for dividing clock frequencies, comprising:
- a frequency divider circuit configured to receive a real number divisor having an integer portion and a decimal portion, the decimal portion comprising a remainder portion and an error portion;
- an error accumulator located within the frequency divider circuit, the error accumulator configured to receive the error portion of the real number divisor;
- and
- a glitch-free multiplexer located within the frequency divider circuit, the glitch-free multiplexer configured to select a clock signal from a plurality of clock signals, wherein the selected clock signal is selected as a function of the remainder portion of the real number divisor.
1 more element
A system for dividing clock frequencies, comprising:
- a frequency divider circuit configured to receive a real number divisor having an integer portion and a decimal portion, the decimal portion comprising a remainder portion and an error portion, the frequency divider circuit further configured to select a clock signal from a plurality of clock signals, wherein the selected clock signal is a function of the integer portion and the remainder portion of the real number divisor, the frequency divider circuit further configured to generate a propagated error, wherein the propagated error represents a part of the decimal portion of the real number that is not reflected in the plurality of clock signals;
- and
- an error accumulator located within the frequency divider circuit, the error accumulator configured to successively add the propagated error.
A system for dividing clock frequencies, comprising:
- a multi-phase clock generator configured to generate a plurality of clock signals;
- a frequency divider circuit configured to receive a real number divisor having an integer portion and a decimal portion, the decimal portion comprising a remainder portion and a non-zero error portion;
- and
- a glitch-free multiplexer located within the frequency divider circuit, the glitch-free multiplexer configured to generate a plurality of clock-select signals, the glitch-free multiplexer further configured to select a clock signal from the generated plurality of clock signals in response to a subset of the generated plurality of clock-select signals.
1 more element
A system for dividing clock frequencies, comprising:
- means for receiving a real number divisor having an integer portion and a decimal portion, the decimal portion comprising a remainder portion and an error portion;
- and
- means for selecting a clock signal from a plurality of clock signals, wherein the selected clock signal is selected as a function of the remainder portion of the real number divisor.
A system for dividing clock frequencies, comprising:
- means for receiving a real number divisor having an integer portion and a decimal portion, the decimal portion comprising a remainder portion and an error portion;
- means for selecting a clock signal from a plurality of clock signals, wherein the selected clock signal is a function of the integer portion and the remainder portion of the real number divisor;
- means for generating a propagated error, wherein the propagated error represents a part of the decimal portion of the real number that is not reflected in the plurality of clock signals;
- and
- means for successively adding the propagated error.
2 more elements
A system for dividing clock frequencies, comprising:
- means for generating a plurality of clock signals;
- means for receiving a real number divisor having an integer portion and a decimal portion, the decimal portion comprising a remainder portion and an error portion;
- and
- means for generating a plurality of clock-select signals;
- means for selecting a clock signal from the generated plurality of clock signals in response to a subset of the generated plurality of clock-select signals.
2 more elements
A method for dividing clock frequencies, comprising the steps of:
- receiving a reference clock signal having a reference clock frequency;
- dividing the reference clock signal by a real number greater than 1 to produce a desired clock signal having a desired clock frequency, the real number having an integer portion and a decimal portion, the decimal portion having a remainder portion and an error portion;
- accumulating the error portion of the real number;
- and
- outputting the desired clock signal.
2 more elements
Dependencies are inferred from the claim text.