Asynchronous timing oscillator re-synchronizer and method

An asynchronous timing oscillator re-synchronizer which enables a high frequency clock used to measure time intervals in a clocked system to be temporarily disabled without significant loss of timing accuracy, comprising:

• a high frequency clock oscillator;
• a high frequency clock buffer connected to said oscillator which, when enabled, makes the output of said oscillator available as a high frequency clock;
• a high frequency clock counter which counts the cycles of said high frequency clock;
• a low frequency clock counter which counts the cycles of a low frequency clock, said high and low frequency clocks used in a clocked system which normally measures time intervals with said high frequency clock;
• a clock ratio register connected to said high and low frequency clock counters and arranged to periodically store a clock ratio given by the number of high frequency clock cycles that occur during a predetermined number of low frequency clock cycles;
• a clock-disable counter connected to receive said low frequency clock and a clock-disable command which indicates that said high frequency clock is to be disabled for a disablement period defined as a specified number y of low frequency clock cycles as inputs;
• a stable time register which stores a value x representing the number of low frequency clock cycles required for the output frequency of said high frequency clock oscillator to become stable after being powered up, said clock-disable counter arranged to, upon receipt of said clock-disable command, load said specified number y, power down said high frequency clock oscillator, disable said buffer, and decrement said loaded number by one for each cycle of said low frequency clock, said clock-disable counter and said stable time register arranged to power said high frequency clock oscillator back up when said clock-disable counter counts down to the value x stored in said stable time register and to re-enable said high frequency clock buffer when y low frequency clock cycles have occurred;
• and
• a missing high frequency clock cycles register which receives said low frequency clock and a signal which indicates that said high frequency clock is disabled as inputs, said missing high frequency clock cycles register arranged to, while said high frequency clock is disabled, periodically increment the value stored in its register by said clock ratio such that the number stored in said missing high frequency clock cycles register when said high frequency clock is re-enabled represents the number of high-frequency clock cycles that would have occurred during said disablement period, said number stored in said missing high frequency clock cycles register at the end of said disablement period provided to said clocked system and enabling said clocked system to be re-synchronized with said high frequency clock.

A method of re-synchronizing a clocked system to a high frequency clock used to measure time intervals after said high frequency clock is temporarily disabled, comprising the steps of:

• providing a high frequency clock and a low frequency clock to a clocked system which normally uses said high frequency clock to measure time intervals;
• determining a clock ratio given by the number of cycles of said high frequency clock that occur for a given number of cycles of said low frequency clock;
• disabling said high frequency clock;
• incrementing a value by said clock ratio for each cycle of said low frequency clock that occurs while said high frequency clock is disabled, said incremented value representing the number of cycles of said high frequency clock that would have occurred while said high frequency clock was disabled;
• re-enabling said high frequency clock;
• and
• providing said incremented value to said clocked system, said incremented value enabling said clocked system to re-synchronize with said high frequency clock.