Semiconductor memory device
AssigneeFujitsu Limited
InventorsMasatomo Hasegawa, Kaoru Mori, Masato Matsumiya
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Abstract
A semiconductor memory device is provided with a clock generation circuit that generates a first clock that has the same frequency and phase as an external clock, and a second clock that has the same frequency as the external clock but a phase a quarter phase shifted, and the first clock and the second clock are supplied to the two DDR-DRAMs as clocks so that the two DDR-DRAMs can operate in a state of being a quarter phase shifted from each other. A data output section outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first or the second clock and brings a data output circuit into a high impedance state for other time periods.
Claims5
A semiconductor memory device, having first and second DDR-DRAMS, in a package, that output data with a fixed phase at the leading edge and trailing edge of a clock, the data input/output lines of the first and the second DDR-DRAMs being connected commonly, comprising:
- a clock generation circuit that generates, from an external clock, a first clock having the same frequency and phase as the external clock and a second clock having the same frequency as the external clock but being a quarter phase shifted, supplies the first clock to the first DDR-DRAM as a clock, and supplies the second clock to the second DDR-DRAM as a clock;
- a data output portion, in the first DDR-DRAM, that outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first clock and brings a data output circuit into a high impedance state for other time periods;
- and
- a data output portion, in the second DDR-DRAM, that outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the second clock and brings a data output circuit into a high impedance state for other time periods.
Dependencies are inferred from the claim text.