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US 6,618,316 B2Granted
Pseudo-static single-ended cache cell
AssigneeIntel Corporation
InventorsSteven K. Hsu, Ram Krishnamurthy
Life of this patent
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Abstract
A cache memory cell comprising a read-access transistor to access the cell, where the read-access transistor is reverse biased when the memory cell is not being read to reduce sub-threshold leakage current.
Claims6
A memory comprising:
- a local bit line;
- and
- a memory cell comprising:
- a read port;
- a read-access transistor having a first source/drain connected to the local bit line, and having a second source/drain and a gate;
- a NAND gate having an output port connected to the second source/drain of the read-access transistor, having a first input port connected to the read port, and having a second input port;
- and
- a static circuit to store a logical state;
- wherein the second input port of the NAND gate is coupled to the static circuit, the second input port of the NAND gate having a voltage responsive to the stored logical state.
6 more elements
A memory cell comprising:
- a read port;
- a read-access transistor having a source/drain and a gate;
- and
- a NAND gate having an output port connected to the source/drain of the read-access transistor, having a first input port connected to the read port, and having a second input port;
- and
- a static circuit to store a logical state;
- wherein the second input port of the NAND gate is coupled to the static circuit, the second input port of the NAND gate having a voltage responsive to the stored logical state.
4 more elements
Dependencies are inferred from the claim text.