US 6,618,315 B2 · Non-volatile, electrically alterable semiconductor memory

Abstract

Non-volatile, electrically alterable semiconductor memory, including at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection circuitry for selecting columns among the plurality of columns, and a write circuit for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block that can be individually erased. The plurality of doped semiconductor regions define a plurality of column packets each one containing a second number of columns equal to or higher than the first number, memory cells belonging to columns of a same column packet being formed in a same doped semiconductor region distinct from the doped semiconductor regions in which memory cells belonging to columns of the other column packets are formed. The column selection circuits are such that within each column packet columns containing memory cells that can be written simultaneously by the write circuit are distributed among the columns of the column packet so as to be at the substantially maximum distance from each other allowable within the column packet.

Claims14

Dependent claims

A non-volatile, electrically alterable semiconductor memory comprising:

at least one array of memory cells arranged in a plurality of rows and a plurality of columns;
a write circuit for simultaneously writing a selected number of memory cells;
a plurality of doped semiconductor regions extending transversely to the rows and dividing the memory cells of each row into a plurality of subsets of memory cells, each subset of memory cells within the same doped semiconductor region defining an independently erasable memory block;
a plurality of column packets, each column packet comprising at least one column of memory cells, the number of columns of memory cells in each column packet being greater than or equal to the selected number of memory cells;
and
a column selection circuit for selecting columns of memory cells such that columns of memory cells comprising memory cells that are simultaneously written by said write circuit are distributed among said plurality of column packets so as to be a maximum distance from one another within each column packet.

3 more elements

A memory comprising:

at least one array of memory cells arranged in a plurality of columns and a plurality of rows;
a write circuit to write a selected number of said memory cells;
a plurality of doped semiconductor regions dividing said at least one array of memory cells into a plurality of subsets of memory cells, each subset of memory cells within a doped semiconductor region comprising an independently erasable memory block;
a plurality of column packets, each column packet comprising at least one column of memory cells, the number of columns of memory cells in each column packet being greater than or equal to the selected number of memory cells;
a row selection circuit for selecting at least one row of memory cells from among said plurality of rows during an erase operation to supply a row erase voltage to the selected at least one row of memory cells;
a column selection circuit for selecting columns of memory cells such that columns of memory cells comprising memory cells written by said write circuit are distributed among said plurality of column packets so as to be a maximum distance from one another within each column packet.

3 more elements

Dependencies are inferred from the claim text.

Non-volatile, electrically alterable semiconductor memory

Life of this patent

Non-volatile, electrically alterable semiconductor memory

Life of this patent

Abstract

Claims14