Method and architecture for reducing the power consumption for memory devices in refresh operations
AssigneeCypress Semiconductor Corporation
InventorsTimothy E. Fiscus, David E. Chapman, Richard M. Parent
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Abstract
A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.
Claims24
A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of:
- enabling said background operations in one or more of said plurality of sections of said memory array when one or more control signals are in a first state and disabling said background operations in said one or more sections when said one or more control signals are in a second state;
- and
- presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said one or more sections.
An apparatus comprising:
- means for enabling a background operation in one or more sections of a memory array when one or more control signals have a first state and disabling said background operation in said one or more sections when said one or more control signals have a second state;
- and
- means for presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said one or more sections.
An apparatus comprising:
- a memory array comprising a plurality of sections, wherein each of said sections comprises (i) a plurality of memory cells and (ii) periphery array circuitry configured to control access to said plurality of memory cells;
- and
- a control circuit configured to present one or more control signals and one or more decoded address signals to said periphery array circuitry of said plurality of sections, wherein a background operation in one or more of said plurality of sections of said memory array is (i) enabled when said one or more control signals are in a first state and (ii) disabled when said one or more control signals are in a second state.
Dependencies are inferred from the claim text.