Self-timed activation logic for memory
AssigneeIntel Corporation
InventorsThu V. Nguyen, Ruban Kanapathippillai
Life of this patent
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Abstract
A self timed logic circuit is used to generate a self timed memory clock to access data in a memory. The self timed memory clock has a periodic pulse which enables circuitry in the memory for a brief period of time over its pulse width. The amount of charge and voltage change, required on bit lines for resolving a bit of data stored in a memory cell during the pulse width of the self timed memory clock, is reduced by using a sensitive sense amplifier so that power can be conserved.
Claims19
A method to lower power consumption during memory access, the method comprising:
- generating a self timed memory clock having periodic pulses;
- enabling an array of sense amplifiers coupled to bit lines of the memory during a narrow pulse width of the periodic pulses;
- and,
- determining the logical state of memory cells coupled to the bit lines during the narrow pulse width of the periodic pulses to lower power consumption.
A self timed logic circuit comprising:
- an odd numbered inverter delay to receive a clock input signal and to generate a delayed inverted clock signal;
- a first NAND gate coupled to the output of the odd numbered inverter delay, the first NAND gate to receive and NAND together the delayed inverted clock signal and the clock input signal and to generate an inverted first memory clock signal having a narrow periodic pulse;
- a first inverter coupled to the first NAND gate, the first inverter to receive and invert the inverted first memory clock signal and to generate a second memory clock signal having a narrow periodic pulse;
- a second NAND gate to receive and NAND together the second memory clock signal and a memory enable signal to generate a third memory clock signal;
- and
- a second inverter to receive and invert the third memory clock signal to generate a fourth memory clock signal having a narrow pulse width.
A memory having reduced power consumption during memory access comprising:
- a memory array having a plurality of memory cells arranged into rows and columns;
- a self timed logic circuit to generate a self timed memory clock signal having a narrow periodic pulse;
- and,
- a row address decoder coupled to the self timed logic circuit to receive the self timed memory clock signal, the row address decoder to generate a word line signal in response to the self timed memory clock signal to access a row of memory cells during the narrow periodic pulse;
- and
- an array of sense amplifiers coupled to bit lines in the columns of memory cells in the memory array, the sense amplifiers to determine if a logical level of a zero or one is stored in the memory cells that arc addressed by the row address decoder, each sense amplifier to receive the self timed memory clock signal to enable differentiation between a voltage level on a negative bit line and a positive bit line and to determine the logical level stored in a memory cell during the narrow periodic pulse.
Dependencies are inferred from the claim text.