Synchronous semiconductor memory device and refresh method thereof

Abstract

In a synchronous semiconductor memory device which provides the refresh cycle optimum for charge retention characteristics without being influenced by production variations, and without requiring much test time to measure characteristics before adjustment of the refresh time, and enables reduction of current consumption in a refresh operation, an output signal from an active pointer circuit which is a phase comparison signal from a DLL circuit is output as a digital signal, and the digital signal is converted by a D/A converter circuit to an analog signal for determining the current value of a constant current circuit, and then, in a measured cycle modification circuit constituting the constant current circuit, the current value responsive to the voltage value of this analog signal is set as the driving current of an oscillation circuit which is a refresh cycle measurement circuit so as to control a driving capability, thereby an oscillation signal for self-refreshing is output.

Dependencies are inferred from the claim text.