Adjustable memory self-timing circuit
AssigneeAnalog Devices, Inc.
InventorsJames E. DeMaris, Michael D. Eby
Life of this patent
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Abstract
A static Random Access Memory (RAM) has a sense enable circuit. A user-determinable number of timing cells produces a timing bit line output in response to a wordline enable input. A sense timing control circuit is triggered by the timing bit line output. The sense timing control circuit produces a sense enable signal for enabling a sensing amplifier to read the logic state of memory cells in communication with the sensing amplifier. A user can change the number of timing cells to optimize operation.
Claims12
A sense enable circuit for a static Random Access Memory (RAM) including a plurality of memory cells, the circuit comprising:
- a user-determinable number of timing cells to produce a timing bit line output in response to a wordline enable input;
- and
- a sense timing control circuit triggered by the timing bit line output to produce a sense enable signal for enabling a sensing amplifier to read the logic state of memory cells in communication with the sensing amplifier.
A sense enable circuit for a static Random Access Memory (RAM) including a plurality of memory cells, the circuit comprising:
- a user-determinable number of timing cells to produce a timing bit line output in response to a wordline enable input;
- and
- means, triggered by the timing bit line output, for producing a sense enable signal for enabling a sensing amplifier to read the logic state of memory cells in communication with the sensing amplifier.
A Random Access Memory (RAM) comprising:
- a plurality of memory cells grouped into rows and columns;
- a sensing amplifier in communication with the memory cells to produce a logic level output representative of the contents of memory cells activated by a wordline input;
- a user-determinable number of timing cells to produce a timing bit line output in response to the wordline enable input;
- and
- a sense timing control circuit triggered by the timing bit line output to produce a sense enable signal for enabling the sensing amplifier to read the logic state of the activated memory cells.
Dependencies are inferred from the claim text.