Integrated circuit, test structure and method for testing integrated circuits

An integrated circuit, comprising:

• memory cells for storing test parameters;
• and
• an electronic circuit for carrying out an operational test and connected to said memory cells, said electronic circuit applying a supply voltage for the integrated circuit and permitting a single write operation to said memory cells and preventing any further writing to said memory cells, said electronic circuit having an input, an output, and a pulse generator with an input and a gate and a flip-flop connected to said pulse generator, said input of said electronic circuit receiving the supply voltage for writing to said memory cells and transmitting the supply voltage to said output for the single write operation to said memory cells, said flip-flop adopting a first state after the supply voltage has been turned on and adopting a second state when said pulse generator outputs a pulse received by said flip-flop on a basis of the control signal applied to said input of said pulse generator, and said gate being transmissive for the control signal in the first state on the basis of an output signal from said flip-flop and being non-transmissive in the second state.

A test structure for a plurality of integrated circuits, comprising:

• a test apparatus, where operating signals for the integrated circuits, can be connected individually by said test apparatus.

A method for testing a plurality of integrated circuits, which comprises the steps of:

• determining test parameters for each of the plurality of integrated circuits by a preliminary test and writing the test parameters determined to memory cells of associated ones of the integrated circuits;
• and
• carrying out a parallel operational test with all the integrated circuits.